diff --git a/cubemx/Core/Inc/dma.h b/cubemx/Core/Inc/dma.h index f1411fa..655402d 100644 --- a/cubemx/Core/Inc/dma.h +++ b/cubemx/Core/Inc/dma.h @@ -1,8 +1,8 @@ /** ****************************************************************************** - * File Name : dma.h - * Description : This file contains all the function prototypes for - * the dma.c file + * @file dma.h + * @brief This file contains all the function prototypes for + * the dma.c file ****************************************************************************** * @attention * @@ -17,11 +17,11 @@ ****************************************************************************** */ /* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __dma_H -#define __dma_H +#ifndef __DMA_H__ +#define __DMA_H__ #ifdef __cplusplus - extern "C" { +extern "C" { #endif /* Includes ------------------------------------------------------------------*/ @@ -47,10 +47,6 @@ void MX_DMA_Init(void); } #endif -#endif /* __dma_H */ - -/** - * @} - */ +#endif /* __DMA_H__ */ /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/cubemx/Core/Inc/gpio.h b/cubemx/Core/Inc/gpio.h index 59eefa8..6b6fe6f 100644 --- a/cubemx/Core/Inc/gpio.h +++ b/cubemx/Core/Inc/gpio.h @@ -1,8 +1,8 @@ /** ****************************************************************************** - * File Name : gpio.h - * Description : This file contains all the functions prototypes for - * the gpio + * @file gpio.h + * @brief This file contains all the function prototypes for + * the gpio.c file ****************************************************************************** * @attention * @@ -16,12 +16,12 @@ * ****************************************************************************** */ - /* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __gpio_H -#define __gpio_H +#ifndef __GPIO_H__ +#define __GPIO_H__ + #ifdef __cplusplus - extern "C" { +extern "C" { #endif /* Includes ------------------------------------------------------------------*/ @@ -44,14 +44,6 @@ void MX_GPIO_Init(void); #ifdef __cplusplus } #endif -#endif /*__ pinoutConfig_H */ - -/** - * @} - */ - -/** - * @} - */ +#endif /*__ GPIO_H__ */ /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/cubemx/Core/Inc/spi.h b/cubemx/Core/Inc/spi.h index b1125a1..18ee8f6 100644 --- a/cubemx/Core/Inc/spi.h +++ b/cubemx/Core/Inc/spi.h @@ -1,8 +1,8 @@ /** ****************************************************************************** - * File Name : SPI.h - * Description : This file provides code for the configuration - * of the SPI instances. + * @file spi.h + * @brief This file contains all the function prototypes for + * the spi.c file ****************************************************************************** * @attention * @@ -17,10 +17,11 @@ ****************************************************************************** */ /* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __spi_H -#define __spi_H +#ifndef __SPI_H__ +#define __SPI_H__ + #ifdef __cplusplus - extern "C" { +extern "C" { #endif /* Includes ------------------------------------------------------------------*/ @@ -45,14 +46,7 @@ void MX_SPI2_Init(void); #ifdef __cplusplus } #endif -#endif /*__ spi_H */ -/** - * @} - */ - -/** - * @} - */ +#endif /* __SPI_H__ */ /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/cubemx/Core/Inc/stm32l1xx_hal_conf.h b/cubemx/Core/Inc/stm32l1xx_hal_conf.h index 32023cf..9b35a13 100644 --- a/cubemx/Core/Inc/stm32l1xx_hal_conf.h +++ b/cubemx/Core/Inc/stm32l1xx_hal_conf.h @@ -99,7 +99,7 @@ * This value is the default MSI range value after Reset. */ #if !defined (MSI_VALUE) - #define MSI_VALUE ((uint32_t)16000000) /*!< Value of the Internal oscillator in Hz*/ + #define MSI_VALUE ((uint32_t)2097000) /*!< Value of the Internal oscillator in Hz*/ #endif /* MSI_VALUE */ /** * @brief Internal High Speed oscillator (HSI) value. diff --git a/cubemx/Core/Src/dma.c b/cubemx/Core/Src/dma.c index 35c81fd..f0f2738 100644 --- a/cubemx/Core/Src/dma.c +++ b/cubemx/Core/Src/dma.c @@ -1,8 +1,8 @@ /** ****************************************************************************** - * File Name : dma.c - * Description : This file provides code for the configuration - * of all the requested memory to memory DMA transfers. + * @file dma.c + * @brief This file provides code for the configuration + * of all the requested memory to memory DMA transfers. ****************************************************************************** * @attention * @@ -55,12 +55,4 @@ void MX_DMA_Init(void) /* USER CODE END 2 */ -/** - * @} - */ - -/** - * @} - */ - /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/cubemx/Core/Src/freertos.c b/cubemx/Core/Src/freertos.c index 026ad17..46bc6af 100644 --- a/cubemx/Core/Src/freertos.c +++ b/cubemx/Core/Src/freertos.c @@ -52,15 +52,15 @@ osThreadId_t defaultTaskHandle; const osThreadAttr_t defaultTask_attributes = { .name = "defaultTask", + .stack_size = 128 * 4, .priority = (osPriority_t) osPriorityNormal, - .stack_size = 128 * 4 }; /* Definitions for sensor */ osThreadId_t sensorHandle; const osThreadAttr_t sensor_attributes = { .name = "sensor", + .stack_size = 512 * 4, .priority = (osPriority_t) osPriorityNormal, - .stack_size = 512 * 4 }; /* Private function prototypes -----------------------------------------------*/ @@ -122,6 +122,10 @@ void MX_FREERTOS_Init(void) { /* add threads, ... */ /* USER CODE END RTOS_THREADS */ + /* USER CODE BEGIN RTOS_EVENTS */ + /* add events, ... */ + /* USER CODE END RTOS_EVENTS */ + } /* USER CODE BEGIN Header_StartDefaultTask */ diff --git a/cubemx/Core/Src/gpio.c b/cubemx/Core/Src/gpio.c index 88171fa..ac0d7a1 100644 --- a/cubemx/Core/Src/gpio.c +++ b/cubemx/Core/Src/gpio.c @@ -1,8 +1,8 @@ /** ****************************************************************************** - * File Name : gpio.c - * Description : This file provides code for the configuration - * of all used GPIO pins. + * @file gpio.c + * @brief This file provides code for the configuration + * of all used GPIO pins. ****************************************************************************** * @attention * @@ -19,6 +19,7 @@ /* Includes ------------------------------------------------------------------*/ #include "gpio.h" + /* USER CODE BEGIN 0 */ /* USER CODE END 0 */ diff --git a/cubemx/Core/Src/spi.c b/cubemx/Core/Src/spi.c index 54e5c12..af3b4e8 100644 --- a/cubemx/Core/Src/spi.c +++ b/cubemx/Core/Src/spi.c @@ -1,8 +1,8 @@ /** ****************************************************************************** - * File Name : SPI.c - * Description : This file provides code for the configuration - * of the SPI instances. + * @file spi.c + * @brief This file provides code for the configuration + * of the SPI instances. ****************************************************************************** * @attention * @@ -32,6 +32,13 @@ DMA_HandleTypeDef hdma_spi2_tx; void MX_SPI2_Init(void) { + /* USER CODE BEGIN SPI2_Init 0 */ + + /* USER CODE END SPI2_Init 0 */ + + /* USER CODE BEGIN SPI2_Init 1 */ + + /* USER CODE END SPI2_Init 1 */ hspi2.Instance = SPI2; hspi2.Init.Mode = SPI_MODE_MASTER; hspi2.Init.Direction = SPI_DIRECTION_2LINES; @@ -48,6 +55,9 @@ void MX_SPI2_Init(void) { Error_Handler(); } + /* USER CODE BEGIN SPI2_Init 2 */ + + /* USER CODE END SPI2_Init 2 */ } diff --git a/cubemx/Core/Src/stm32l1xx_hal_msp.c b/cubemx/Core/Src/stm32l1xx_hal_msp.c index e4fc821..598c83a 100644 --- a/cubemx/Core/Src/stm32l1xx_hal_msp.c +++ b/cubemx/Core/Src/stm32l1xx_hal_msp.c @@ -72,6 +72,8 @@ void HAL_MspInit(void) __HAL_RCC_PWR_CLK_ENABLE(); /* System interrupt init*/ + /* PendSV_IRQn interrupt configuration */ + HAL_NVIC_SetPriority(PendSV_IRQn, 15, 0); /* USER CODE BEGIN MspInit 1 */ diff --git a/cubemx/Core/Src/stm32l1xx_hal_timebase_tim.c b/cubemx/Core/Src/stm32l1xx_hal_timebase_tim.c index 96bf328..5b9ab43 100644 --- a/cubemx/Core/Src/stm32l1xx_hal_timebase_tim.c +++ b/cubemx/Core/Src/stm32l1xx_hal_timebase_tim.c @@ -50,6 +50,7 @@ HAL_StatusTypeDef HAL_InitTick(uint32_t TickPriority) /* Enable the TIM2 global Interrupt */ HAL_NVIC_EnableIRQ(TIM2_IRQn); + /* Enable TIM2 clock */ __HAL_RCC_TIM2_CLK_ENABLE(); @@ -58,9 +59,8 @@ HAL_StatusTypeDef HAL_InitTick(uint32_t TickPriority) /* Compute TIM2 clock */ uwTimclock = HAL_RCC_GetPCLK1Freq(); - /* Compute the prescaler value to have TIM2 counter clock equal to 1MHz */ - uwPrescalerValue = (uint32_t) ((uwTimclock / 1000000) - 1); + uwPrescalerValue = (uint32_t) ((uwTimclock / 1000000U) - 1U); /* Initialize TIM2 */ htim2.Instance = TIM2; @@ -71,10 +71,11 @@ HAL_StatusTypeDef HAL_InitTick(uint32_t TickPriority) + ClockDivision = 0 + Counter direction = Up */ - htim2.Init.Period = (1000000 / 1000) - 1; + htim2.Init.Period = (1000000U / 1000U) - 1U; htim2.Init.Prescaler = uwPrescalerValue; htim2.Init.ClockDivision = 0; htim2.Init.CounterMode = TIM_COUNTERMODE_UP; + if(HAL_TIM_Base_Init(&htim2) == HAL_OK) { /* Start the TIM time Base generation in interrupt mode */ diff --git a/cubemx/Drivers/CMSIS/Device/ST/STM32L1xx/Include/stm32l152xc.h b/cubemx/Drivers/CMSIS/Device/ST/STM32L1xx/Include/stm32l152xc.h index f851cc7..6aa8cb6 100644 --- a/cubemx/Drivers/CMSIS/Device/ST/STM32L1xx/Include/stm32l152xc.h +++ b/cubemx/Drivers/CMSIS/Device/ST/STM32L1xx/Include/stm32l152xc.h @@ -805,6 +805,15 @@ typedef struct * @{ */ + /** @addtogroup Hardware_Constant_Definition + * @{ + */ +#define LSI_STARTUP_TIME 200U /*!< LSI Maximum startup time in us */ + + /** + * @} + */ + /** @addtogroup Peripheral_Registers_Bits_Definition * @{ */ @@ -3002,6 +3011,10 @@ typedef struct /* (FLASH, DATA_EEPROM, OB) */ /* */ /******************************************************************************/ +/* + * @brief Specific device feature definitions (not present on all devices in the STM32L1 serie) + */ +#define FLASH_CUT3 /******************* Bit definition for FLASH_ACR register ******************/ #define FLASH_ACR_LATENCY_Pos (0U) @@ -5841,8 +5854,8 @@ typedef struct #define SYSCFG_EXTICR1_EXTI3_PC (0x00002000U) /*!< PC[3] pin */ #define SYSCFG_EXTICR1_EXTI3_PD (0x00003000U) /*!< PD[3] pin */ #define SYSCFG_EXTICR1_EXTI3_PE (0x00004000U) /*!< PE[3] pin */ -#define SYSCFG_EXTICR1_EXTI3_PF (0x00003000U) /*!< PF[3] pin */ -#define SYSCFG_EXTICR1_EXTI3_PG (0x00004000U) /*!< PG[3] pin */ +#define SYSCFG_EXTICR1_EXTI3_PF (0x00006000U) /*!< PF[3] pin */ +#define SYSCFG_EXTICR1_EXTI3_PG (0x00007000U) /*!< PG[3] pin */ /***************** Bit definition for SYSCFG_EXTICR2 register *****************/ #define SYSCFG_EXTICR2_EXTI4_Pos (0U) @@ -6017,7 +6030,7 @@ typedef struct #define SYSCFG_EXTICR4_EXTI15_PE (0x00004000U) /*!< PE[15] pin */ #define SYSCFG_EXTICR4_EXTI15_PF (0x00006000U) /*!< PF[15] pin */ #define SYSCFG_EXTICR4_EXTI15_PG (0x00007000U) /*!< PG[15] pin */ - + /******************************************************************************/ /* */ /* Routing Interface (RI) */ diff --git a/cubemx/Drivers/CMSIS/Device/ST/STM32L1xx/Include/stm32l1xx.h b/cubemx/Drivers/CMSIS/Device/ST/STM32L1xx/Include/stm32l1xx.h index 289efd7..e0f876a 100644 --- a/cubemx/Drivers/CMSIS/Device/ST/STM32L1xx/Include/stm32l1xx.h +++ b/cubemx/Drivers/CMSIS/Device/ST/STM32L1xx/Include/stm32l1xx.h @@ -70,19 +70,19 @@ /* #define STM32L151xC */ /*!< STM32L151CC, STM32L151UC, STM32L151RC and STM32L151VC */ /* #define STM32L151xCA */ /*!< STM32L151RC-A, STM32L151VC-A, STM32L151QC and STM32L151ZC */ /* #define STM32L151xD */ /*!< STM32L151QD, STM32L151RD, STM32L151VD & STM32L151ZD */ - /* #define STM32L151xDX */ /*!< STM32L151VD-X Devices */ + /* #define STM32L151xDX */ /*!< STM32L151VD-X Devices */ /* #define STM32L151xE */ /*!< STM32L151QE, STM32L151RE, STM32L151VE and STM32L151ZE */ /* #define STM32L152xB */ /*!< STM32L152C6, STM32L152R6, STM32L152C8, STM32L152R8, STM32L152V8, STM32L152CB, STM32L152RB and STM32L152VB */ /* #define STM32L152xBA */ /*!< STM32L152C6-A, STM32L152R6-A, STM32L152C8-A, STM32L152R8-A, STM32L152V8-A, STM32L152CB-A, STM32L152RB-A and STM32L152VB-A */ /* #define STM32L152xC */ /*!< STM32L152CC, STM32L152UC, STM32L152RC and STM32L152VC */ /* #define STM32L152xCA */ /*!< STM32L152RC-A, STM32L152VC-A, STM32L152QC and STM32L152ZC */ /* #define STM32L152xD */ /*!< STM32L152QD, STM32L152RD, STM32L152VD and STM32L152ZD */ - /* #define STM32L152xDX */ /*!< STM32L152VD-X Devices */ + /* #define STM32L152xDX */ /*!< STM32L152VD-X Devices */ /* #define STM32L152xE */ /*!< STM32L152QE, STM32L152RE, STM32L152VE and STM32L152ZE */ /* #define STM32L162xC */ /*!< STM32L162RC and STM32L162VC */ /* #define STM32L162xCA */ /*!< STM32L162RC-A, STM32L162VC-A, STM32L162QC and STM32L162ZC */ /* #define STM32L162xD */ /*!< STM32L162QD, STM32L162RD, STM32L162VD and STM32L162ZD */ - /* #define STM32L162xDX */ /*!< STM32L162VD-X Devices */ + /* #define STM32L162xDX */ /*!< STM32L162VD-X Devices */ /* #define STM32L162xE */ /*!< STM32L162RE, STM32L162VE and STM32L162ZE */ #endif @@ -100,11 +100,11 @@ #endif /* USE_HAL_DRIVER */ /** - * @brief CMSIS Device version number V2.3.1 + * @brief CMSIS Device version number V2.3.2 */ #define __STM32L1xx_CMSIS_VERSION_MAIN (0x02) /*!< [31:24] main version */ #define __STM32L1xx_CMSIS_VERSION_SUB1 (0x03) /*!< [23:16] sub1 version */ -#define __STM32L1xx_CMSIS_VERSION_SUB2 (0x01) /*!< [15:8] sub2 version */ +#define __STM32L1xx_CMSIS_VERSION_SUB2 (0x02) /*!< [15:8] sub2 version */ #define __STM32L1xx_CMSIS_VERSION_RC (0x00) /*!< [7:0] release candidate */ #define __STM32L1xx_CMSIS_VERSION ((__STM32L1xx_CMSIS_VERSION_MAIN << 24)\ |(__STM32L1xx_CMSIS_VERSION_SUB1 << 16)\ @@ -215,6 +215,61 @@ typedef enum #define MODIFY_REG(REG, CLEARMASK, SETMASK) WRITE_REG((REG), (((READ_REG(REG)) & (~(CLEARMASK))) | (SETMASK))) +/* Use of CMSIS compiler intrinsics for register exclusive access */ +/* Atomic 32-bit register access macro to set one or several bits */ +#define ATOMIC_SET_BIT(REG, BIT) \ + do { \ + uint32_t val; \ + do { \ + val = __LDREXW((__IO uint32_t *)&(REG)) | (BIT); \ + } while ((__STREXW(val,(__IO uint32_t *)&(REG))) != 0U); \ + } while(0) + +/* Atomic 32-bit register access macro to clear one or several bits */ +#define ATOMIC_CLEAR_BIT(REG, BIT) \ + do { \ + uint32_t val; \ + do { \ + val = __LDREXW((__IO uint32_t *)&(REG)) & ~(BIT); \ + } while ((__STREXW(val,(__IO uint32_t *)&(REG))) != 0U); \ + } while(0) + +/* Atomic 32-bit register access macro to clear and set one or several bits */ +#define ATOMIC_MODIFY_REG(REG, CLEARMSK, SETMASK) \ + do { \ + uint32_t val; \ + do { \ + val = (__LDREXW((__IO uint32_t *)&(REG)) & ~(CLEARMSK)) | (SETMASK); \ + } while ((__STREXW(val,(__IO uint32_t *)&(REG))) != 0U); \ + } while(0) + +/* Atomic 16-bit register access macro to set one or several bits */ +#define ATOMIC_SETH_BIT(REG, BIT) \ + do { \ + uint16_t val; \ + do { \ + val = __LDREXH((__IO uint16_t *)&(REG)) | (BIT); \ + } while ((__STREXH(val,(__IO uint16_t *)&(REG))) != 0U); \ + } while(0) + +/* Atomic 16-bit register access macro to clear one or several bits */ +#define ATOMIC_CLEARH_BIT(REG, BIT) \ + do { \ + uint16_t val; \ + do { \ + val = __LDREXH((__IO uint16_t *)&(REG)) & ~(BIT); \ + } while ((__STREXH(val,(__IO uint16_t *)&(REG))) != 0U); \ + } while(0) + +/* Atomic 16-bit register access macro to clear and set one or several bits */ +#define ATOMIC_MODIFYH_REG(REG, CLEARMSK, SETMASK) \ + do { \ + uint16_t val; \ + do { \ + val = (__LDREXH((__IO uint16_t *)&(REG)) & ~(CLEARMSK)) | (SETMASK); \ + } while ((__STREXH(val,(__IO uint16_t *)&(REG))) != 0U); \ + } while(0) + #define POSITION_VAL(VAL) (__CLZ(__RBIT(VAL))) diff --git a/cubemx/Drivers/STM32L1xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h b/cubemx/Drivers/STM32L1xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h index b358058..04413aa 100644 --- a/cubemx/Drivers/STM32L1xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h +++ b/cubemx/Drivers/STM32L1xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h @@ -23,7 +23,7 @@ #define STM32_HAL_LEGACY #ifdef __cplusplus - extern "C" { +extern "C" { #endif /* Includes ------------------------------------------------------------------*/ @@ -38,7 +38,6 @@ #define AES_CLEARFLAG_CCF CRYP_CLEARFLAG_CCF #define AES_CLEARFLAG_RDERR CRYP_CLEARFLAG_RDERR #define AES_CLEARFLAG_WRERR CRYP_CLEARFLAG_WRERR - /** * @} */ @@ -211,6 +210,15 @@ * @} */ +/** @defgroup CRC_Aliases CRC API aliases + * @{ + */ +#define HAL_CRC_Input_Data_Reverse HAL_CRCEx_Input_Data_Reverse /*!< Aliased to HAL_CRCEx_Input_Data_Reverse for inter STM32 series compatibility */ +#define HAL_CRC_Output_Data_Reverse HAL_CRCEx_Output_Data_Reverse /*!< Aliased to HAL_CRCEx_Output_Data_Reverse for inter STM32 series compatibility */ +/** + * @} + */ + /** @defgroup HAL_CRC_Aliased_Defines HAL CRC Aliased Defines maintained for legacy purpose * @{ */ @@ -383,7 +391,6 @@ #define DAC_TRIGGER_LP2_OUT DAC_TRIGGER_LPTIM2_OUT #endif /* STM32H7 */ - /** * @} */ @@ -471,14 +478,14 @@ #define OB_BOOT_ENTRY_FORCED_FLASH OB_BOOT_LOCK_ENABLE #endif #if defined(STM32H7) -#define FLASH_FLAG_SNECCE_BANK1RR FLASH_FLAG_SNECCERR_BANK1 -#define FLASH_FLAG_DBECCE_BANK1RR FLASH_FLAG_DBECCERR_BANK1 -#define FLASH_FLAG_STRBER_BANK1R FLASH_FLAG_STRBERR_BANK1 -#define FLASH_FLAG_SNECCE_BANK2RR FLASH_FLAG_SNECCERR_BANK2 -#define FLASH_FLAG_DBECCE_BANK2RR FLASH_FLAG_DBECCERR_BANK2 -#define FLASH_FLAG_STRBER_BANK2R FLASH_FLAG_STRBERR_BANK2 -#define FLASH_FLAG_WDW FLASH_FLAG_WBNE -#define OB_WRP_SECTOR_All OB_WRP_SECTOR_ALL +#define FLASH_FLAG_SNECCE_BANK1RR FLASH_FLAG_SNECCERR_BANK1 +#define FLASH_FLAG_DBECCE_BANK1RR FLASH_FLAG_DBECCERR_BANK1 +#define FLASH_FLAG_STRBER_BANK1R FLASH_FLAG_STRBERR_BANK1 +#define FLASH_FLAG_SNECCE_BANK2RR FLASH_FLAG_SNECCERR_BANK2 +#define FLASH_FLAG_DBECCE_BANK2RR FLASH_FLAG_DBECCERR_BANK2 +#define FLASH_FLAG_STRBER_BANK2R FLASH_FLAG_STRBERR_BANK2 +#define FLASH_FLAG_WDW FLASH_FLAG_WBNE +#define OB_WRP_SECTOR_All OB_WRP_SECTOR_ALL #endif /* STM32H7 */ /** @@ -522,6 +529,7 @@ #define HAL_SYSCFG_EnableIOAnalogSwitchVDD HAL_SYSCFG_EnableIOSwitchVDD #define HAL_SYSCFG_DisableIOAnalogSwitchVDD HAL_SYSCFG_DisableIOSwitchVDD #endif /* STM32G4 */ + /** * @} */ @@ -596,24 +604,24 @@ #define GPIO_AF1_LPTIM GPIO_AF1_LPTIM1 #define GPIO_AF2_LPTIM GPIO_AF2_LPTIM1 -#if defined(STM32L0) || defined(STM32L4) || defined(STM32F4) || defined(STM32F2) || defined(STM32F7) || defined(STM32G4) || defined(STM32H7) +#if defined(STM32L0) || defined(STM32L4) || defined(STM32F4) || defined(STM32F2) || defined(STM32F7) || defined(STM32G4) || defined(STM32H7) || defined(STM32WB) #define GPIO_SPEED_LOW GPIO_SPEED_FREQ_LOW #define GPIO_SPEED_MEDIUM GPIO_SPEED_FREQ_MEDIUM #define GPIO_SPEED_FAST GPIO_SPEED_FREQ_HIGH #define GPIO_SPEED_HIGH GPIO_SPEED_FREQ_VERY_HIGH -#endif /* STM32L0 || STM32L4 || STM32F4 || STM32F2 || STM32F7 || STM32G4 || STM32H7*/ +#endif /* STM32L0 || STM32L4 || STM32F4 || STM32F2 || STM32F7 || STM32G4 || STM32H7 || STM32WB*/ #if defined(STM32L1) - #define GPIO_SPEED_VERY_LOW GPIO_SPEED_FREQ_LOW - #define GPIO_SPEED_LOW GPIO_SPEED_FREQ_MEDIUM - #define GPIO_SPEED_MEDIUM GPIO_SPEED_FREQ_HIGH - #define GPIO_SPEED_HIGH GPIO_SPEED_FREQ_VERY_HIGH +#define GPIO_SPEED_VERY_LOW GPIO_SPEED_FREQ_LOW +#define GPIO_SPEED_LOW GPIO_SPEED_FREQ_MEDIUM +#define GPIO_SPEED_MEDIUM GPIO_SPEED_FREQ_HIGH +#define GPIO_SPEED_HIGH GPIO_SPEED_FREQ_VERY_HIGH #endif /* STM32L1 */ #if defined(STM32F0) || defined(STM32F3) || defined(STM32F1) - #define GPIO_SPEED_LOW GPIO_SPEED_FREQ_LOW - #define GPIO_SPEED_MEDIUM GPIO_SPEED_FREQ_MEDIUM - #define GPIO_SPEED_HIGH GPIO_SPEED_FREQ_HIGH +#define GPIO_SPEED_LOW GPIO_SPEED_FREQ_LOW +#define GPIO_SPEED_MEDIUM GPIO_SPEED_FREQ_MEDIUM +#define GPIO_SPEED_HIGH GPIO_SPEED_FREQ_HIGH #endif /* STM32F0 || STM32F3 || STM32F1 */ #define GPIO_AF6_DFSDM GPIO_AF6_DFSDM1 @@ -774,49 +782,6 @@ #define HRTIM_EVENTSRC_3 (HRTIM_EECR1_EE1SRC_1) #define HRTIM_EVENTSRC_4 (HRTIM_EECR1_EE1SRC_1 | HRTIM_EECR1_EE1SRC_0) -/** @brief Constants defining the events that can be selected to configure the - * set/reset crossbar of a timer output - */ -#define HRTIM_OUTPUTSET_TIMEV_1 (HRTIM_SET1R_TIMEVNT1) -#define HRTIM_OUTPUTSET_TIMEV_2 (HRTIM_SET1R_TIMEVNT2) -#define HRTIM_OUTPUTSET_TIMEV_3 (HRTIM_SET1R_TIMEVNT3) -#define HRTIM_OUTPUTSET_TIMEV_4 (HRTIM_SET1R_TIMEVNT4) -#define HRTIM_OUTPUTSET_TIMEV_5 (HRTIM_SET1R_TIMEVNT5) -#define HRTIM_OUTPUTSET_TIMEV_6 (HRTIM_SET1R_TIMEVNT6) -#define HRTIM_OUTPUTSET_TIMEV_7 (HRTIM_SET1R_TIMEVNT7) -#define HRTIM_OUTPUTSET_TIMEV_8 (HRTIM_SET1R_TIMEVNT8) -#define HRTIM_OUTPUTSET_TIMEV_9 (HRTIM_SET1R_TIMEVNT9) - -#define HRTIM_OUTPUTRESET_TIMEV_1 (HRTIM_RST1R_TIMEVNT1) -#define HRTIM_OUTPUTRESET_TIMEV_2 (HRTIM_RST1R_TIMEVNT2) -#define HRTIM_OUTPUTRESET_TIMEV_3 (HRTIM_RST1R_TIMEVNT3) -#define HRTIM_OUTPUTRESET_TIMEV_4 (HRTIM_RST1R_TIMEVNT4) -#define HRTIM_OUTPUTRESET_TIMEV_5 (HRTIM_RST1R_TIMEVNT5) -#define HRTIM_OUTPUTRESET_TIMEV_6 (HRTIM_RST1R_TIMEVNT6) -#define HRTIM_OUTPUTRESET_TIMEV_7 (HRTIM_RST1R_TIMEVNT7) -#define HRTIM_OUTPUTRESET_TIMEV_8 (HRTIM_RST1R_TIMEVNT8) -#define HRTIM_OUTPUTRESET_TIMEV_9 (HRTIM_RST1R_TIMEVNT9) - -/** @brief Constants defining the event filtering applied to external events - * by a timer - */ -#define HRTIM_TIMEVENTFILTER_NONE (0x00000000U) -#define HRTIM_TIMEVENTFILTER_BLANKINGCMP1 (HRTIM_EEFR1_EE1FLTR_0) -#define HRTIM_TIMEVENTFILTER_BLANKINGCMP2 (HRTIM_EEFR1_EE1FLTR_1) -#define HRTIM_TIMEVENTFILTER_BLANKINGCMP3 (HRTIM_EEFR1_EE1FLTR_1 | HRTIM_EEFR1_EE1FLTR_0) -#define HRTIM_TIMEVENTFILTER_BLANKINGCMP4 (HRTIM_EEFR1_EE1FLTR_2) -#define HRTIM_TIMEVENTFILTER_BLANKINGFLTR1 (HRTIM_EEFR1_EE1FLTR_2 | HRTIM_EEFR1_EE1FLTR_0) -#define HRTIM_TIMEVENTFILTER_BLANKINGFLTR2 (HRTIM_EEFR1_EE1FLTR_2 | HRTIM_EEFR1_EE1FLTR_1) -#define HRTIM_TIMEVENTFILTER_BLANKINGFLTR3 (HRTIM_EEFR1_EE1FLTR_2 | HRTIM_EEFR1_EE1FLTR_1 | HRTIM_EEFR1_EE1FLTR_0) -#define HRTIM_TIMEVENTFILTER_BLANKINGFLTR4 (HRTIM_EEFR1_EE1FLTR_3) -#define HRTIM_TIMEVENTFILTER_BLANKINGFLTR5 (HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_0) -#define HRTIM_TIMEVENTFILTER_BLANKINGFLTR6 (HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_1) -#define HRTIM_TIMEVENTFILTER_BLANKINGFLTR7 (HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_1 | HRTIM_EEFR1_EE1FLTR_0) -#define HRTIM_TIMEVENTFILTER_BLANKINGFLTR8 (HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_2) -#define HRTIM_TIMEVENTFILTER_WINDOWINGCMP2 (HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_2 | HRTIM_EEFR1_EE1FLTR_0) -#define HRTIM_TIMEVENTFILTER_WINDOWINGCMP3 (HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_2 | HRTIM_EEFR1_EE1FLTR_1) -#define HRTIM_TIMEVENTFILTER_WINDOWINGTIM (HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_2 | HRTIM_EEFR1_EE1FLTR_1 | HRTIM_EEFR1_EE1FLTR_0) - /** @brief Constants defining the DLL calibration periods (in micro seconds) */ #define HRTIM_CALIBRATIONRATE_7300 0x00000000U @@ -969,6 +934,11 @@ #define HAL_OPAMP_MSP_DEINIT_CB_ID HAL_OPAMP_MSPDEINIT_CB_ID #endif +#if defined(STM32L4) || defined(STM32L5) +#define OPAMP_POWERMODE_NORMAL OPAMP_POWERMODE_NORMALPOWER +#elif defined(STM32G4) +#define OPAMP_POWERMODE_NORMAL OPAMP_POWERMODE_NORMALSPEED +#endif /** * @} @@ -980,15 +950,15 @@ #define I2S_STANDARD_PHILLIPS I2S_STANDARD_PHILIPS #if defined(STM32H7) - #define I2S_IT_TXE I2S_IT_TXP - #define I2S_IT_RXNE I2S_IT_RXP +#define I2S_IT_TXE I2S_IT_TXP +#define I2S_IT_RXNE I2S_IT_RXP - #define I2S_FLAG_TXE I2S_FLAG_TXP - #define I2S_FLAG_RXNE I2S_FLAG_RXP +#define I2S_FLAG_TXE I2S_FLAG_TXP +#define I2S_FLAG_RXNE I2S_FLAG_RXP #endif #if defined(STM32F7) - #define I2S_CLOCK_SYSCLK I2S_CLOCK_PLL +#define I2S_CLOCK_SYSCLK I2S_CLOCK_PLL #endif /** * @} @@ -1023,7 +993,7 @@ /** * @} */ - + /** @defgroup HAL_RTC_Aliased_Defines HAL RTC Aliased Defines maintained for legacy purpose * @{ */ @@ -1123,16 +1093,16 @@ #if defined(STM32H7) - #define SPI_FLAG_TXE SPI_FLAG_TXP - #define SPI_FLAG_RXNE SPI_FLAG_RXP +#define SPI_FLAG_TXE SPI_FLAG_TXP +#define SPI_FLAG_RXNE SPI_FLAG_RXP - #define SPI_IT_TXE SPI_IT_TXP - #define SPI_IT_RXNE SPI_IT_RXP +#define SPI_IT_TXE SPI_IT_TXP +#define SPI_IT_RXNE SPI_IT_RXP - #define SPI_FRLVL_EMPTY SPI_RX_FIFO_0PACKET - #define SPI_FRLVL_QUARTER_FULL SPI_RX_FIFO_1PACKET - #define SPI_FRLVL_HALF_FULL SPI_RX_FIFO_2PACKET - #define SPI_FRLVL_FULL SPI_RX_FIFO_3PACKET +#define SPI_FRLVL_EMPTY SPI_RX_FIFO_0PACKET +#define SPI_FRLVL_QUARTER_FULL SPI_RX_FIFO_1PACKET +#define SPI_FRLVL_HALF_FULL SPI_RX_FIFO_2PACKET +#define SPI_FRLVL_FULL SPI_RX_FIFO_3PACKET #endif /* STM32H7 */ @@ -1418,6 +1388,20 @@ */ #endif /* STM32L4 || STM32F7 || STM32F4 || STM32H7 */ +#if defined(STM32L4) || defined(STM32F7) || defined(STM32F427xx) || defined(STM32F437xx) \ + || defined(STM32F429xx) || defined(STM32F439xx) || defined(STM32F469xx) || defined(STM32F479xx) \ + || defined(STM32H7) +/** @defgroup DMA2D_Aliases DMA2D API Aliases + * @{ + */ +#define HAL_DMA2D_DisableCLUT HAL_DMA2D_CLUTLoading_Abort /*!< Aliased to HAL_DMA2D_CLUTLoading_Abort + for compatibility with legacy code */ +/** + * @} + */ + +#endif /* STM32L4 || STM32F7 || STM32F4 || STM32H7 */ + /** @defgroup HAL_PPP_Aliased_Defines HAL PPP Aliased Defines maintained for legacy purpose * @{ */ @@ -1436,6 +1420,16 @@ * @} */ +#if !defined(STM32F2) +/** @defgroup HASH_alias HASH API alias + * @{ + */ +#define HAL_HASHEx_IRQHandler HAL_HASH_IRQHandler /*!< Redirection for compatibility with legacy code */ +/** + * + * @} + */ +#endif /* STM32F2 */ /** @defgroup HAL_HASH_Aliased_Functions HAL HASH Aliased Functions maintained for legacy purpose * @{ */ @@ -1459,7 +1453,7 @@ #define HASH_HMACKeyType_ShortKey HASH_HMAC_KEYTYPE_SHORTKEY #define HASH_HMACKeyType_LongKey HASH_HMAC_KEYTYPE_LONGKEY -#if defined(STM32L4) || defined(STM32L5) || defined(STM32F4) || defined(STM32F7) || defined(STM32H7) +#if defined(STM32L4) || defined(STM32L5) || defined(STM32F2) || defined(STM32F4) || defined(STM32F7) || defined(STM32H7) #define HAL_HASH_MD5_Accumulate HAL_HASH_MD5_Accmlt #define HAL_HASH_MD5_Accumulate_End HAL_HASH_MD5_Accmlt_End @@ -1481,7 +1475,7 @@ #define HAL_HASHEx_SHA256_Accumulate_IT HAL_HASHEx_SHA256_Accmlt_IT #define HAL_HASHEx_SHA256_Accumulate_End_IT HAL_HASHEx_SHA256_Accmlt_End_IT -#endif /* STM32L4 || STM32L5 || STM32F4 || STM32F7 || STM32H7 */ +#endif /* STM32L4 || STM32L5 || STM32F2 || STM32F4 || STM32F7 || STM32H7 */ /** * @} */ @@ -1495,7 +1489,8 @@ #define HAL_DisableDBGStopMode HAL_DBGMCU_DisableDBGStopMode #define HAL_EnableDBGStandbyMode HAL_DBGMCU_EnableDBGStandbyMode #define HAL_DisableDBGStandbyMode HAL_DBGMCU_DisableDBGStandbyMode -#define HAL_DBG_LowPowerConfig(Periph, cmd) (((cmd)==ENABLE)? HAL_DBGMCU_DBG_EnableLowPowerConfig(Periph) : HAL_DBGMCU_DBG_DisableLowPowerConfig(Periph)) +#define HAL_DBG_LowPowerConfig(Periph, cmd) (((cmd\ + )==ENABLE)? HAL_DBGMCU_DBG_EnableLowPowerConfig(Periph) : HAL_DBGMCU_DBG_DisableLowPowerConfig(Periph)) #define HAL_VREFINT_OutputSelect HAL_SYSCFG_VREFINT_OutputSelect #define HAL_Lock_Cmd(cmd) (((cmd)==ENABLE) ? HAL_SYSCFG_Enable_Lock_VREFINT() : HAL_SYSCFG_Disable_Lock_VREFINT()) #if defined(STM32L0) @@ -1503,7 +1498,8 @@ #define HAL_VREFINT_Cmd(cmd) (((cmd)==ENABLE)? HAL_SYSCFG_EnableVREFINT() : HAL_SYSCFG_DisableVREFINT()) #endif #define HAL_ADC_EnableBuffer_Cmd(cmd) (((cmd)==ENABLE) ? HAL_ADCEx_EnableVREFINT() : HAL_ADCEx_DisableVREFINT()) -#define HAL_ADC_EnableBufferSensor_Cmd(cmd) (((cmd)==ENABLE) ? HAL_ADCEx_EnableVREFINTTempSensor() : HAL_ADCEx_DisableVREFINTTempSensor()) +#define HAL_ADC_EnableBufferSensor_Cmd(cmd) (((cmd\ + )==ENABLE) ? HAL_ADCEx_EnableVREFINTTempSensor() : HAL_ADCEx_DisableVREFINTTempSensor()) #if defined(STM32H7A3xx) || defined(STM32H7B3xx) || defined(STM32H7B0xx) || defined(STM32H7A3xxQ) || defined(STM32H7B3xxQ) || defined(STM32H7B0xxQ) #define HAL_EnableSRDomainDBGStopMode HAL_EnableDomain3DBGStopMode #define HAL_DisableSRDomainDBGStopMode HAL_DisableDomain3DBGStopMode @@ -1526,9 +1522,9 @@ #define HAL_DATA_EEPROMEx_Erase HAL_FLASHEx_DATAEEPROM_Erase #define HAL_DATA_EEPROMEx_Program HAL_FLASHEx_DATAEEPROM_Program - /** +/** * @} - */ + */ /** @defgroup HAL_I2C_Aliased_Functions HAL I2C Aliased Functions maintained for legacy purpose * @{ @@ -1538,7 +1534,8 @@ #define HAL_FMPI2CEx_AnalogFilter_Config HAL_FMPI2CEx_ConfigAnalogFilter #define HAL_FMPI2CEx_DigitalFilter_Config HAL_FMPI2CEx_ConfigDigitalFilter -#define HAL_I2CFastModePlusConfig(SYSCFG_I2CFastModePlus, cmd) (((cmd)==ENABLE)? HAL_I2CEx_EnableFastModePlus(SYSCFG_I2CFastModePlus): HAL_I2CEx_DisableFastModePlus(SYSCFG_I2CFastModePlus)) +#define HAL_I2CFastModePlusConfig(SYSCFG_I2CFastModePlus, cmd) (((cmd\ + )==ENABLE)? HAL_I2CEx_EnableFastModePlus(SYSCFG_I2CFastModePlus): HAL_I2CEx_DisableFastModePlus(SYSCFG_I2CFastModePlus)) #if defined(STM32H7) || defined(STM32WB) || defined(STM32G0) || defined(STM32F0) || defined(STM32F1) || defined(STM32F2) || defined(STM32F3) || defined(STM32F4) || defined(STM32F7) || defined(STM32L0) || defined(STM32L4) || defined(STM32L5) || defined(STM32G4) || defined(STM32L1) #define HAL_I2C_Master_Sequential_Transmit_IT HAL_I2C_Master_Seq_Transmit_IT @@ -1563,9 +1560,9 @@ #define HAL_FMPI2C_Slave_Sequential_Transmit_DMA HAL_FMPI2C_Slave_Seq_Transmit_DMA #define HAL_FMPI2C_Slave_Sequential_Receive_DMA HAL_FMPI2C_Slave_Seq_Receive_DMA #endif /* STM32F4 */ - /** +/** * @} - */ + */ /** @defgroup HAL_PWR_Aliased HAL PWR Aliased maintained for legacy purpose * @{ @@ -1620,9 +1617,9 @@ #define PWR_MODE_EVT PWR_PVD_MODE_NORMAL - /** +/** * @} - */ + */ /** @defgroup HAL_SMBUS_Aliased_Functions HAL SMBUS Aliased Functions maintained for legacy purpose * @{ @@ -1871,15 +1868,15 @@ #define __HAL_FREEZE_RTC_DBGMCU __HAL_DBGMCU_FREEZE_RTC #define __HAL_UNFREEZE_RTC_DBGMCU __HAL_DBGMCU_UNFREEZE_RTC #if defined(STM32H7) - #define __HAL_FREEZE_WWDG_DBGMCU __HAL_DBGMCU_FREEZE_WWDG1 - #define __HAL_UNFREEZE_WWDG_DBGMCU __HAL_DBGMCU_UnFreeze_WWDG1 - #define __HAL_FREEZE_IWDG_DBGMCU __HAL_DBGMCU_FREEZE_IWDG1 - #define __HAL_UNFREEZE_IWDG_DBGMCU __HAL_DBGMCU_UnFreeze_IWDG1 +#define __HAL_FREEZE_WWDG_DBGMCU __HAL_DBGMCU_FREEZE_WWDG1 +#define __HAL_UNFREEZE_WWDG_DBGMCU __HAL_DBGMCU_UnFreeze_WWDG1 +#define __HAL_FREEZE_IWDG_DBGMCU __HAL_DBGMCU_FREEZE_IWDG1 +#define __HAL_UNFREEZE_IWDG_DBGMCU __HAL_DBGMCU_UnFreeze_IWDG1 #else - #define __HAL_FREEZE_WWDG_DBGMCU __HAL_DBGMCU_FREEZE_WWDG - #define __HAL_UNFREEZE_WWDG_DBGMCU __HAL_DBGMCU_UNFREEZE_WWDG - #define __HAL_FREEZE_IWDG_DBGMCU __HAL_DBGMCU_FREEZE_IWDG - #define __HAL_UNFREEZE_IWDG_DBGMCU __HAL_DBGMCU_UNFREEZE_IWDG +#define __HAL_FREEZE_WWDG_DBGMCU __HAL_DBGMCU_FREEZE_WWDG +#define __HAL_UNFREEZE_WWDG_DBGMCU __HAL_DBGMCU_UNFREEZE_WWDG +#define __HAL_FREEZE_IWDG_DBGMCU __HAL_DBGMCU_FREEZE_IWDG +#define __HAL_UNFREEZE_IWDG_DBGMCU __HAL_DBGMCU_UNFREEZE_IWDG #endif /* STM32H7 */ #define __HAL_FREEZE_I2C1_TIMEOUT_DBGMCU __HAL_DBGMCU_FREEZE_I2C1_TIMEOUT #define __HAL_UNFREEZE_I2C1_TIMEOUT_DBGMCU __HAL_DBGMCU_UNFREEZE_I2C1_TIMEOUT @@ -2090,8 +2087,8 @@ */ #define IS_DAC_WAVE(WAVE) (((WAVE) == DAC_WAVE_NONE) || \ - ((WAVE) == DAC_WAVE_NOISE)|| \ - ((WAVE) == DAC_WAVE_TRIANGLE)) + ((WAVE) == DAC_WAVE_NOISE)|| \ + ((WAVE) == DAC_WAVE_TRIANGLE)) /** * @} @@ -2147,7 +2144,7 @@ #define IS_I2S_INSTANCE_EXT IS_I2S_ALL_INSTANCE_EXT #if defined(STM32H7) - #define __HAL_I2S_CLEAR_FREFLAG __HAL_I2S_CLEAR_TIFREFLAG +#define __HAL_I2S_CLEAR_FREFLAG __HAL_I2S_CLEAR_TIFREFLAG #endif /** @@ -2284,7 +2281,8 @@ #define RCC_StopWakeUpClock_HSI RCC_STOP_WAKEUPCLOCK_HSI #define HAL_RCC_CCSCallback HAL_RCC_CSSCallback -#define HAL_RC48_EnableBuffer_Cmd(cmd) (((cmd)==ENABLE) ? HAL_RCCEx_EnableHSI48_VREFINT() : HAL_RCCEx_DisableHSI48_VREFINT()) +#define HAL_RC48_EnableBuffer_Cmd(cmd) (((cmd\ + )==ENABLE) ? HAL_RCCEx_EnableHSI48_VREFINT() : HAL_RCCEx_DisableHSI48_VREFINT()) #define __ADC_CLK_DISABLE __HAL_RCC_ADC_CLK_DISABLE #define __ADC_CLK_ENABLE __HAL_RCC_ADC_CLK_ENABLE @@ -3252,7 +3250,7 @@ #define RCC_MCOSOURCE_PLLCLK_NODIV RCC_MCO1SOURCE_PLLCLK #define RCC_MCOSOURCE_PLLCLK_DIV2 RCC_MCO1SOURCE_PLLCLK_DIV2 -#if defined(STM32L4) || defined(STM32WB) || defined(STM32G0) || defined(STM32G4) || defined(STM32L5) +#if defined(STM32L4) || defined(STM32WB) || defined(STM32G0) || defined(STM32G4) || defined(STM32L5) || defined(STM32WL) #define RCC_RTCCLKSOURCE_NO_CLK RCC_RTCCLKSOURCE_NONE #else #define RCC_RTCCLKSOURCE_NONE RCC_RTCCLKSOURCE_NO_CLK @@ -3381,7 +3379,7 @@ /** @defgroup HAL_RTC_Aliased_Macros HAL RTC Aliased Macros maintained for legacy purpose * @{ */ -#if defined (STM32G0) || defined (STM32L5) || defined (STM32L412xx) || defined (STM32L422xx) || defined (STM32L4P5xx) || defined (STM32L4Q5xx) || defined (STM32G4) +#if defined (STM32G0) || defined (STM32L5) || defined (STM32L412xx) || defined (STM32L422xx) || defined (STM32L4P5xx) || defined (STM32L4Q5xx) || defined (STM32G4) || defined (STM32WL) #else #define __HAL_RTC_CLEAR_FLAG __HAL_RTC_EXTI_CLEAR_FLAG #endif @@ -3401,19 +3399,19 @@ #else #define __HAL_RTC_EXTI_CLEAR_FLAG(__EXTI_LINE__) (((__EXTI_LINE__) == RTC_EXTI_LINE_ALARM_EVENT) ? __HAL_RTC_ALARM_EXTI_CLEAR_FLAG() : \ (((__EXTI_LINE__) == RTC_EXTI_LINE_WAKEUPTIMER_EVENT) ? __HAL_RTC_WAKEUPTIMER_EXTI_CLEAR_FLAG() : \ - __HAL_RTC_TAMPER_TIMESTAMP_EXTI_CLEAR_FLAG())) + __HAL_RTC_TAMPER_TIMESTAMP_EXTI_CLEAR_FLAG())) #define __HAL_RTC_EXTI_ENABLE_IT(__EXTI_LINE__) (((__EXTI_LINE__) == RTC_EXTI_LINE_ALARM_EVENT) ? __HAL_RTC_ALARM_EXTI_ENABLE_IT() : \ - (((__EXTI_LINE__) == RTC_EXTI_LINE_WAKEUPTIMER_EVENT) ? __HAL_RTC_WAKEUPTIMER_EXTI_ENABLE_IT() : \ - __HAL_RTC_TAMPER_TIMESTAMP_EXTI_ENABLE_IT())) + (((__EXTI_LINE__) == RTC_EXTI_LINE_WAKEUPTIMER_EVENT) ? __HAL_RTC_WAKEUPTIMER_EXTI_ENABLE_IT() : \ + __HAL_RTC_TAMPER_TIMESTAMP_EXTI_ENABLE_IT())) #define __HAL_RTC_EXTI_DISABLE_IT(__EXTI_LINE__) (((__EXTI_LINE__) == RTC_EXTI_LINE_ALARM_EVENT) ? __HAL_RTC_ALARM_EXTI_DISABLE_IT() : \ - (((__EXTI_LINE__) == RTC_EXTI_LINE_WAKEUPTIMER_EVENT) ? __HAL_RTC_WAKEUPTIMER_EXTI_DISABLE_IT() : \ - __HAL_RTC_TAMPER_TIMESTAMP_EXTI_DISABLE_IT())) + (((__EXTI_LINE__) == RTC_EXTI_LINE_WAKEUPTIMER_EVENT) ? __HAL_RTC_WAKEUPTIMER_EXTI_DISABLE_IT() : \ + __HAL_RTC_TAMPER_TIMESTAMP_EXTI_DISABLE_IT())) #define __HAL_RTC_EXTI_GET_FLAG(__EXTI_LINE__) (((__EXTI_LINE__) == RTC_EXTI_LINE_ALARM_EVENT) ? __HAL_RTC_ALARM_EXTI_GET_FLAG() : \ - (((__EXTI_LINE__) == RTC_EXTI_LINE_WAKEUPTIMER_EVENT) ? __HAL_RTC_WAKEUPTIMER_EXTI_GET_FLAG() : \ - __HAL_RTC_TAMPER_TIMESTAMP_EXTI_GET_FLAG())) + (((__EXTI_LINE__) == RTC_EXTI_LINE_WAKEUPTIMER_EVENT) ? __HAL_RTC_WAKEUPTIMER_EXTI_GET_FLAG() : \ + __HAL_RTC_TAMPER_TIMESTAMP_EXTI_GET_FLAG())) #define __HAL_RTC_EXTI_GENERATE_SWIT(__EXTI_LINE__) (((__EXTI_LINE__) == RTC_EXTI_LINE_ALARM_EVENT) ? __HAL_RTC_ALARM_EXTI_GENERATE_SWIT() : \ - (((__EXTI_LINE__) == RTC_EXTI_LINE_WAKEUPTIMER_EVENT) ? __HAL_RTC_WAKEUPTIMER_EXTI_GENERATE_SWIT() : \ - __HAL_RTC_TAMPER_TIMESTAMP_EXTI_GENERATE_SWIT())) + (((__EXTI_LINE__) == RTC_EXTI_LINE_WAKEUPTIMER_EVENT) ? __HAL_RTC_WAKEUPTIMER_EXTI_GENERATE_SWIT() : \ + __HAL_RTC_TAMPER_TIMESTAMP_EXTI_GENERATE_SWIT())) #endif /* STM32F1 */ #define IS_ALARM IS_RTC_ALARM @@ -3438,13 +3436,17 @@ * @} */ -/** @defgroup HAL_SD_Aliased_Macros HAL SD Aliased Macros maintained for legacy purpose +/** @defgroup HAL_SD_Aliased_Macros HAL SD/MMC Aliased Macros maintained for legacy purpose * @{ */ #define SD_OCR_CID_CSD_OVERWRIETE SD_OCR_CID_CSD_OVERWRITE #define SD_CMD_SD_APP_STAUS SD_CMD_SD_APP_STATUS +#define eMMC_HIGH_VOLTAGE_RANGE EMMC_HIGH_VOLTAGE_RANGE +#define eMMC_DUAL_VOLTAGE_RANGE EMMC_DUAL_VOLTAGE_RANGE +#define eMMC_LOW_VOLTAGE_RANGE EMMC_LOW_VOLTAGE_RANGE + #if defined(STM32F4) || defined(STM32F2) #define SD_SDMMC_DISABLED SD_SDIO_DISABLED #define SD_SDMMC_FUNCTION_BUSY SD_SDIO_FUNCTION_BUSY @@ -3597,6 +3599,13 @@ #define __HAL_USART_GETCLOCKSOURCE USART_GETCLOCKSOURCE #define __USART_GETCLOCKSOURCE USART_GETCLOCKSOURCE +#if defined(STM32F0) || defined(STM32F3) || defined(STM32F7) +#define USART_OVERSAMPLING_16 0x00000000U +#define USART_OVERSAMPLING_8 USART_CR1_OVER8 + +#define IS_USART_OVERSAMPLING(__SAMPLING__) (((__SAMPLING__) == USART_OVERSAMPLING_16) || \ + ((__SAMPLING__) == USART_OVERSAMPLING_8)) +#endif /* STM32F0 || STM32F3 || STM32F7 */ /** * @} */ diff --git a/cubemx/Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_exti.h b/cubemx/Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_exti.h index d26087f..8780cae 100644 --- a/cubemx/Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_exti.h +++ b/cubemx/Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_exti.h @@ -218,19 +218,19 @@ typedef struct /** @defgroup EXTI_Private_Macros EXTI Private Macros * @{ */ -#define IS_EXTI_LINE(__LINE__) ((((__LINE__) & ~(EXTI_PROPERTY_MASK | EXTI_PIN_MASK)) == 0x00u) && \ - ((((__LINE__) & EXTI_PROPERTY_MASK) == EXTI_CONFIG) || \ - (((__LINE__) & EXTI_PROPERTY_MASK) == EXTI_GPIO)) && \ - (((__LINE__) & EXTI_PIN_MASK) < EXTI_LINE_NB)) +#define IS_EXTI_LINE(__EXTI_LINE__) ((((__EXTI_LINE__) & ~(EXTI_PROPERTY_MASK | EXTI_PIN_MASK)) == 0x00u) && \ + ((((__EXTI_LINE__) & EXTI_PROPERTY_MASK) == EXTI_CONFIG) || \ + (((__EXTI_LINE__) & EXTI_PROPERTY_MASK) == EXTI_GPIO)) && \ + (((__EXTI_LINE__) & EXTI_PIN_MASK) < EXTI_LINE_NB)) -#define IS_EXTI_MODE(__LINE__) ((((__LINE__) & EXTI_MODE_MASK) != 0x00u) && \ - (((__LINE__) & ~EXTI_MODE_MASK) == 0x00u)) +#define IS_EXTI_MODE(__EXTI_LINE__) ((((__EXTI_LINE__) & EXTI_MODE_MASK) != 0x00u) && \ + (((__EXTI_LINE__) & ~EXTI_MODE_MASK) == 0x00u)) -#define IS_EXTI_TRIGGER(__LINE__) (((__LINE__) & ~EXTI_TRIGGER_MASK) == 0x00u) +#define IS_EXTI_TRIGGER(__EXTI_LINE__) (((__EXTI_LINE__) & ~EXTI_TRIGGER_MASK) == 0x00u) -#define IS_EXTI_PENDING_EDGE(__LINE__) ((__LINE__) == EXTI_TRIGGER_RISING_FALLING) +#define IS_EXTI_PENDING_EDGE(__EXTI_LINE__) ((__EXTI_LINE__) == EXTI_TRIGGER_RISING_FALLING) -#define IS_EXTI_CONFIG_LINE(__LINE__) (((__LINE__) & EXTI_CONFIG) != 0x00u) +#define IS_EXTI_CONFIG_LINE(__EXTI_LINE__) (((__EXTI_LINE__) & EXTI_CONFIG) != 0x00u) #if !defined (GPIOE) #define IS_EXTI_GPIO_PORT(__PORT__) (((__PORT__) == EXTI_GPIOA) || \ diff --git a/cubemx/Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_flash.h b/cubemx/Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_flash.h index 4fe9f2a..9e65c63 100644 --- a/cubemx/Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_flash.h +++ b/cubemx/Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_flash.h @@ -121,7 +121,11 @@ typedef struct * @{ */ -#define FLASH_SIZE (uint32_t)((*((uint32_t *)FLASHSIZE_BASE)&0xFFFFU) * 1024U) +#if defined (FLASH_CUT1) || defined (FLASH_CUT2) +#define FLASH_SIZE (uint32_t)((*((uint32_t *)FLASHSIZE_BASE)&0xFFU) * 1024U) +#else /*FLASH_CUT3 || FLASH_CUT4 || FLASH_CUT5 || FLASH_CUT6*/ +#define FLASH_SIZE (uint32_t)((*((uint32_t *)FLASHSIZE_BASE)&0xFFFFU) * 1024U) +#endif #define FLASH_PAGE_SIZE (256U) /*!< FLASH Page Size in bytes */ /** diff --git a/cubemx/Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_gpio.h b/cubemx/Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_gpio.h index 8aab770..a1863af 100644 --- a/cubemx/Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_gpio.h +++ b/cubemx/Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_gpio.h @@ -110,29 +110,28 @@ typedef enum /** @defgroup GPIO_mode GPIO mode * @brief GPIO Configuration Mode - * Elements values convention: 0xX0yz00YZ - * - X : GPIO mode or EXTI Mode - * - y : External IT or Event trigger detection - * - z : IO configuration on External IT or Event - * - Y : Output type (Push Pull or Open Drain) - * - Z : IO Direction mode (Input, Output, Alternate or Analog) + * Elements values convention: 0x00WX00YZ + * - W : EXTI trigger detection on 3 bits + * - X : EXTI mode (IT or Event) on 2 bits + * - Y : Output type (Push Pull or Open Drain) on 1 bit + * - Z : GPIO mode (Input, Output, Alternate or Analog) on 2 bits * @{ - */ -#define GPIO_MODE_INPUT (0x00000000U) /*!< Input Floating Mode */ -#define GPIO_MODE_OUTPUT_PP (0x00000001U) /*!< Output Push Pull Mode */ -#define GPIO_MODE_OUTPUT_OD (0x00000011U) /*!< Output Open Drain Mode */ -#define GPIO_MODE_AF_PP (0x00000002U) /*!< Alternate Function Push Pull Mode */ -#define GPIO_MODE_AF_OD (0x00000012U) /*!< Alternate Function Open Drain Mode */ + */ +#define GPIO_MODE_INPUT MODE_INPUT /*!< Input Floating Mode */ +#define GPIO_MODE_OUTPUT_PP (MODE_OUTPUT | OUTPUT_PP) /*!< Output Push Pull Mode */ +#define GPIO_MODE_OUTPUT_OD (MODE_OUTPUT | OUTPUT_OD) /*!< Output Open Drain Mode */ +#define GPIO_MODE_AF_PP (MODE_AF | OUTPUT_PP) /*!< Alternate Function Push Pull Mode */ +#define GPIO_MODE_AF_OD (MODE_AF | OUTPUT_OD) /*!< Alternate Function Open Drain Mode */ -#define GPIO_MODE_ANALOG (0x00000003U) /*!< Analog Mode */ - -#define GPIO_MODE_IT_RISING (0x10110000U) /*!< External Interrupt Mode with Rising edge trigger detection */ -#define GPIO_MODE_IT_FALLING (0x10210000U) /*!< External Interrupt Mode with Falling edge trigger detection */ -#define GPIO_MODE_IT_RISING_FALLING (0x10310000U) /*!< External Interrupt Mode with Rising/Falling edge trigger detection */ - -#define GPIO_MODE_EVT_RISING (0x10120000U) /*!< External Event Mode with Rising edge trigger detection */ -#define GPIO_MODE_EVT_FALLING (0x10220000U) /*!< External Event Mode with Falling edge trigger detection */ -#define GPIO_MODE_EVT_RISING_FALLING (0x10320000U) /*!< External Event Mode with Rising/Falling edge trigger detection */ +#define GPIO_MODE_ANALOG MODE_ANALOG /*!< Analog Mode */ + +#define GPIO_MODE_IT_RISING (MODE_INPUT | EXTI_IT | TRIGGER_RISING) /*!< External Interrupt Mode with Rising edge trigger detection */ +#define GPIO_MODE_IT_FALLING (MODE_INPUT | EXTI_IT | TRIGGER_FALLING) /*!< External Interrupt Mode with Falling edge trigger detection */ +#define GPIO_MODE_IT_RISING_FALLING (MODE_INPUT | EXTI_IT | TRIGGER_RISING | TRIGGER_FALLING) /*!< External Interrupt Mode with Rising/Falling edge trigger detection */ + +#define GPIO_MODE_EVT_RISING (MODE_INPUT | EXTI_EVT | TRIGGER_RISING) /*!< External Event Mode with Rising edge trigger detection */ +#define GPIO_MODE_EVT_FALLING (MODE_INPUT | EXTI_EVT | TRIGGER_FALLING) /*!< External Event Mode with Falling edge trigger detection */ +#define GPIO_MODE_EVT_RISING_FALLING (MODE_INPUT | EXTI_EVT | TRIGGER_RISING | TRIGGER_FALLING) /*!< External Event Mode with Rising/Falling edge trigger detection */ /** * @} @@ -171,7 +170,24 @@ typedef enum /** @defgroup GPIO_Private_Constants GPIO Private Constants * @{ */ - +#define GPIO_MODE_Pos 0U +#define GPIO_MODE (0x3UL << GPIO_MODE_Pos) +#define MODE_INPUT (0x0UL << GPIO_MODE_Pos) +#define MODE_OUTPUT (0x1UL << GPIO_MODE_Pos) +#define MODE_AF (0x2UL << GPIO_MODE_Pos) +#define MODE_ANALOG (0x3UL << GPIO_MODE_Pos) +#define OUTPUT_TYPE_Pos 4U +#define OUTPUT_TYPE (0x1UL << OUTPUT_TYPE_Pos) +#define OUTPUT_PP (0x0UL << OUTPUT_TYPE_Pos) +#define OUTPUT_OD (0x1UL << OUTPUT_TYPE_Pos) +#define EXTI_MODE_Pos 16U +#define EXTI_MODE (0x3UL << EXTI_MODE_Pos) +#define EXTI_IT (0x1UL << EXTI_MODE_Pos) +#define EXTI_EVT (0x2UL << EXTI_MODE_Pos) +#define TRIGGER_MODE_Pos 20U +#define TRIGGER_MODE (0x7UL << TRIGGER_MODE_Pos) +#define TRIGGER_RISING (0x1UL << TRIGGER_MODE_Pos) +#define TRIGGER_FALLING (0x2UL << TRIGGER_MODE_Pos) /** * @} */ diff --git a/cubemx/Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_tim.h b/cubemx/Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_tim.h index d2e5900..b00ae36 100644 --- a/cubemx/Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_tim.h +++ b/cubemx/Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_tim.h @@ -184,7 +184,8 @@ typedef struct uint32_t ClearInputPolarity; /*!< TIM Clear Input polarity This parameter can be a value of @ref TIM_ClearInput_Polarity */ uint32_t ClearInputPrescaler; /*!< TIM Clear Input prescaler - This parameter must be 0: When OCRef clear feature is used with ETR source, ETR prescaler must be off */ + This parameter must be 0: When OCRef clear feature is used with ETR source, + ETR prescaler must be off */ uint32_t ClearInputFilter; /*!< TIM Clear Input filter This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */ } TIM_ClearInputConfigTypeDef; @@ -529,10 +530,8 @@ typedef void (*pTIM_CallbackTypeDef)(TIM_HandleTypeDef *htim); /*!< pointer to /** @defgroup TIM_Input_Capture_Selection TIM Input Capture Selection * @{ */ -#define TIM_ICSELECTION_DIRECTTI TIM_CCMR1_CC1S_0 /*!< TIM Input 1, 2, 3 or 4 is selected to be - connected to IC1, IC2, IC3 or IC4, respectively */ -#define TIM_ICSELECTION_INDIRECTTI TIM_CCMR1_CC1S_1 /*!< TIM Input 1, 2, 3 or 4 is selected to be - connected to IC2, IC1, IC4 or IC3, respectively */ +#define TIM_ICSELECTION_DIRECTTI TIM_CCMR1_CC1S_0 /*!< TIM Input 1, 2, 3 or 4 is selected to be connected to IC1, IC2, IC3 or IC4, respectively */ +#define TIM_ICSELECTION_INDIRECTTI TIM_CCMR1_CC1S_1 /*!< TIM Input 1, 2, 3 or 4 is selected to be connected to IC2, IC1, IC4 or IC3, respectively */ #define TIM_ICSELECTION_TRC TIM_CCMR1_CC1S /*!< TIM Input 1, 2, 3 or 4 is selected to be connected to TRC */ /** * @} @@ -785,24 +784,24 @@ typedef void (*pTIM_CallbackTypeDef)(TIM_HandleTypeDef *htim); /*!< pointer to /** @defgroup TIM_DMA_Burst_Length TIM DMA Burst Length * @{ */ -#define TIM_DMABURSTLENGTH_1TRANSFER 0x00000000U /*!< The transfer is done to 1 register starting trom TIMx_CR1 + TIMx_DCR.DBA */ -#define TIM_DMABURSTLENGTH_2TRANSFERS 0x00000100U /*!< The transfer is done to 2 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */ -#define TIM_DMABURSTLENGTH_3TRANSFERS 0x00000200U /*!< The transfer is done to 3 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */ -#define TIM_DMABURSTLENGTH_4TRANSFERS 0x00000300U /*!< The transfer is done to 4 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */ -#define TIM_DMABURSTLENGTH_5TRANSFERS 0x00000400U /*!< The transfer is done to 5 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */ -#define TIM_DMABURSTLENGTH_6TRANSFERS 0x00000500U /*!< The transfer is done to 6 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */ -#define TIM_DMABURSTLENGTH_7TRANSFERS 0x00000600U /*!< The transfer is done to 7 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */ -#define TIM_DMABURSTLENGTH_8TRANSFERS 0x00000700U /*!< The transfer is done to 8 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */ -#define TIM_DMABURSTLENGTH_9TRANSFERS 0x00000800U /*!< The transfer is done to 9 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */ -#define TIM_DMABURSTLENGTH_10TRANSFERS 0x00000900U /*!< The transfer is done to 10 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */ -#define TIM_DMABURSTLENGTH_11TRANSFERS 0x00000A00U /*!< The transfer is done to 11 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */ -#define TIM_DMABURSTLENGTH_12TRANSFERS 0x00000B00U /*!< The transfer is done to 12 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */ -#define TIM_DMABURSTLENGTH_13TRANSFERS 0x00000C00U /*!< The transfer is done to 13 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */ -#define TIM_DMABURSTLENGTH_14TRANSFERS 0x00000D00U /*!< The transfer is done to 14 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */ -#define TIM_DMABURSTLENGTH_15TRANSFERS 0x00000E00U /*!< The transfer is done to 15 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */ -#define TIM_DMABURSTLENGTH_16TRANSFERS 0x00000F00U /*!< The transfer is done to 16 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */ -#define TIM_DMABURSTLENGTH_17TRANSFERS 0x00001000U /*!< The transfer is done to 17 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */ -#define TIM_DMABURSTLENGTH_18TRANSFERS 0x00001100U /*!< The transfer is done to 18 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */ +#define TIM_DMABURSTLENGTH_1TRANSFER 0x00000000U /*!< The transfer is done to 1 register starting from TIMx_CR1 + TIMx_DCR.DBA */ +#define TIM_DMABURSTLENGTH_2TRANSFERS 0x00000100U /*!< The transfer is done to 2 registers starting from TIMx_CR1 + TIMx_DCR.DBA */ +#define TIM_DMABURSTLENGTH_3TRANSFERS 0x00000200U /*!< The transfer is done to 3 registers starting from TIMx_CR1 + TIMx_DCR.DBA */ +#define TIM_DMABURSTLENGTH_4TRANSFERS 0x00000300U /*!< The transfer is done to 4 registers starting from TIMx_CR1 + TIMx_DCR.DBA */ +#define TIM_DMABURSTLENGTH_5TRANSFERS 0x00000400U /*!< The transfer is done to 5 registers starting from TIMx_CR1 + TIMx_DCR.DBA */ +#define TIM_DMABURSTLENGTH_6TRANSFERS 0x00000500U /*!< The transfer is done to 6 registers starting from TIMx_CR1 + TIMx_DCR.DBA */ +#define TIM_DMABURSTLENGTH_7TRANSFERS 0x00000600U /*!< The transfer is done to 7 registers starting from TIMx_CR1 + TIMx_DCR.DBA */ +#define TIM_DMABURSTLENGTH_8TRANSFERS 0x00000700U /*!< The transfer is done to 8 registers starting from TIMx_CR1 + TIMx_DCR.DBA */ +#define TIM_DMABURSTLENGTH_9TRANSFERS 0x00000800U /*!< The transfer is done to 9 registers starting from TIMx_CR1 + TIMx_DCR.DBA */ +#define TIM_DMABURSTLENGTH_10TRANSFERS 0x00000900U /*!< The transfer is done to 10 registers starting from TIMx_CR1 + TIMx_DCR.DBA */ +#define TIM_DMABURSTLENGTH_11TRANSFERS 0x00000A00U /*!< The transfer is done to 11 registers starting from TIMx_CR1 + TIMx_DCR.DBA */ +#define TIM_DMABURSTLENGTH_12TRANSFERS 0x00000B00U /*!< The transfer is done to 12 registers starting from TIMx_CR1 + TIMx_DCR.DBA */ +#define TIM_DMABURSTLENGTH_13TRANSFERS 0x00000C00U /*!< The transfer is done to 13 registers starting from TIMx_CR1 + TIMx_DCR.DBA */ +#define TIM_DMABURSTLENGTH_14TRANSFERS 0x00000D00U /*!< The transfer is done to 14 registers starting from TIMx_CR1 + TIMx_DCR.DBA */ +#define TIM_DMABURSTLENGTH_15TRANSFERS 0x00000E00U /*!< The transfer is done to 15 registers starting from TIMx_CR1 + TIMx_DCR.DBA */ +#define TIM_DMABURSTLENGTH_16TRANSFERS 0x00000F00U /*!< The transfer is done to 16 registers starting from TIMx_CR1 + TIMx_DCR.DBA */ +#define TIM_DMABURSTLENGTH_17TRANSFERS 0x00001000U /*!< The transfer is done to 17 registers starting from TIMx_CR1 + TIMx_DCR.DBA */ +#define TIM_DMABURSTLENGTH_18TRANSFERS 0x00001100U /*!< The transfer is done to 18 registers starting from TIMx_CR1 + TIMx_DCR.DBA */ /** * @} */ @@ -1021,8 +1020,8 @@ typedef void (*pTIM_CallbackTypeDef)(TIM_HandleTypeDef *htim); /*!< pointer to * @brief Indicates whether or not the TIM Counter is used as downcounter. * @param __HANDLE__ TIM handle. * @retval False (Counter used as upcounter) or True (Counter used as downcounter) - * @note This macro is particularly useful to get the counting mode when the timer operates in Center-aligned mode or Encoder -mode. + * @note This macro is particularly useful to get the counting mode when the timer operates in Center-aligned mode + * or Encoder mode. */ #define __HAL_TIM_IS_TIM_COUNTING_DOWN(__HANDLE__) (((__HANDLE__)->Instance->CR1 &(TIM_CR1_DIR)) == (TIM_CR1_DIR)) @@ -1096,7 +1095,8 @@ mode. #define __HAL_TIM_GET_CLOCKDIVISION(__HANDLE__) ((__HANDLE__)->Instance->CR1 & TIM_CR1_CKD) /** - * @brief Set the TIM Input Capture prescaler on runtime without calling another time HAL_TIM_IC_ConfigChannel() function. + * @brief Set the TIM Input Capture prescaler on runtime without calling another time HAL_TIM_IC_ConfigChannel() + * function. * @param __HANDLE__ TIM handle. * @param __CHANNEL__ TIM Channels to be configured. * This parameter can be one of the following values: @@ -1539,7 +1539,7 @@ mode. ((__CHANNEL__) == TIM_CHANNEL_2) ? (__HANDLE__)->ChannelState[1] :\ ((__CHANNEL__) == TIM_CHANNEL_3) ? (__HANDLE__)->ChannelState[2] :\ (__HANDLE__)->ChannelState[3]) - + #define TIM_CHANNEL_STATE_SET(__HANDLE__, __CHANNEL__, __CHANNEL_STATE__) \ (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->ChannelState[0] = (__CHANNEL_STATE__)) :\ ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->ChannelState[1] = (__CHANNEL_STATE__)) :\ @@ -1725,14 +1725,14 @@ HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchro_IT(TIM_HandleTypeDef *htim, TIM_Sla HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, uint32_t BurstRequestSrc, uint32_t *BurstBuffer, uint32_t BurstLength); HAL_StatusTypeDef HAL_TIM_DMABurst_MultiWriteStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, - uint32_t BurstRequestSrc, uint32_t *BurstBuffer, uint32_t BurstLength, - uint32_t DataLength); + uint32_t BurstRequestSrc, uint32_t *BurstBuffer, + uint32_t BurstLength, uint32_t DataLength); HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStop(TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc); HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, uint32_t BurstRequestSrc, uint32_t *BurstBuffer, uint32_t BurstLength); HAL_StatusTypeDef HAL_TIM_DMABurst_MultiReadStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, - uint32_t BurstRequestSrc, uint32_t *BurstBuffer, uint32_t BurstLength, - uint32_t DataLength); + uint32_t BurstRequestSrc, uint32_t *BurstBuffer, + uint32_t BurstLength, uint32_t DataLength); HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStop(TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc); HAL_StatusTypeDef HAL_TIM_GenerateEvent(TIM_HandleTypeDef *htim, uint32_t EventSource); uint32_t HAL_TIM_ReadCapturedValue(TIM_HandleTypeDef *htim, uint32_t Channel); @@ -1796,8 +1796,6 @@ HAL_TIM_DMABurstStateTypeDef HAL_TIM_DMABurstState(TIM_HandleTypeDef *htim); /** @defgroup TIM_Private_Functions TIM Private Functions * @{ */ -void TIM_DMADelayPulseCplt(DMA_HandleTypeDef *hdma); -void TIM_DMADelayPulseHalfCplt(DMA_HandleTypeDef *hdma); void TIM_DMAError(DMA_HandleTypeDef *hdma); void TIM_DMACaptureCplt(DMA_HandleTypeDef *hdma); void TIM_DMACaptureHalfCplt(DMA_HandleTypeDef *hdma); diff --git a/cubemx/Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal.c b/cubemx/Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal.c index ea4601a..24ff0d3 100644 --- a/cubemx/Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal.c +++ b/cubemx/Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal.c @@ -54,11 +54,11 @@ */ /** - * @brief STM32L1xx HAL Driver version number V1.4.3 + * @brief STM32L1xx HAL Driver version number V1.4.4 */ #define __STM32L1xx_HAL_VERSION_MAIN (0x01) /*!< [31:24] main version */ #define __STM32L1xx_HAL_VERSION_SUB1 (0x04) /*!< [23:16] sub1 version */ -#define __STM32L1xx_HAL_VERSION_SUB2 (0x03) /*!< [15:8] sub2 version */ +#define __STM32L1xx_HAL_VERSION_SUB2 (0x04) /*!< [15:8] sub2 version */ #define __STM32L1xx_HAL_VERSION_RC (0x00) /*!< [7:0] release candidate */ #define __STM32L1xx_HAL_VERSION ((__STM32L1xx_HAL_VERSION_MAIN << 24)\ |(__STM32L1xx_HAL_VERSION_SUB1 << 16)\ diff --git a/cubemx/Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_exti.c b/cubemx/Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_exti.c index 3173ca6..337abfa 100644 --- a/cubemx/Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_exti.c +++ b/cubemx/Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_exti.c @@ -276,6 +276,10 @@ HAL_StatusTypeDef HAL_EXTI_GetConfigLine(EXTI_HandleTypeDef *hexti, EXTI_ConfigT pExtiConfig->Mode |= EXTI_MODE_EVENT; } + /* Get default Trigger and GPIOSel configuration */ + pExtiConfig->Trigger = EXTI_TRIGGER_NONE; + pExtiConfig->GPIOSel = 0x00u; + /* 2] Get trigger for configurable lines : rising */ if ((pExtiConfig->Line & EXTI_CONFIG) != 0x00u) { @@ -284,10 +288,6 @@ HAL_StatusTypeDef HAL_EXTI_GetConfigLine(EXTI_HandleTypeDef *hexti, EXTI_ConfigT { pExtiConfig->Trigger = EXTI_TRIGGER_RISING; } - else - { - pExtiConfig->Trigger = EXTI_TRIGGER_NONE; - } /* Get falling configuration */ /* Check if configuration of selected line is enable */ @@ -304,16 +304,6 @@ HAL_StatusTypeDef HAL_EXTI_GetConfigLine(EXTI_HandleTypeDef *hexti, EXTI_ConfigT regval = SYSCFG->EXTICR[linepos >> 2u]; pExtiConfig->GPIOSel = ((regval << (SYSCFG_EXTICR1_EXTI1_Pos * (3uL - (linepos & 0x03u)))) >> 24); } - else - { - pExtiConfig->GPIOSel = 0x00u; - } - } - else - { - /* No Trigger selected */ - pExtiConfig->Trigger = EXTI_TRIGGER_NONE; - pExtiConfig->GPIOSel = 0x00u; } return HAL_OK; diff --git a/cubemx/Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_flash.c b/cubemx/Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_flash.c index aab5749..66d08eb 100644 --- a/cubemx/Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_flash.c +++ b/cubemx/Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_flash.c @@ -650,6 +650,7 @@ HAL_StatusTypeDef FLASH_WaitForLastOperation(uint32_t Timeout) #if defined(FLASH_SR_OPTVERRUSR) __HAL_FLASH_GET_FLAG(FLASH_FLAG_OPTVERRUSR) || #endif /* FLASH_SR_OPTVERRUSR */ + __HAL_FLASH_GET_FLAG(FLASH_FLAG_SIZERR) || __HAL_FLASH_GET_FLAG(FLASH_FLAG_PGAERR)) { /*Save the error code*/ @@ -700,10 +701,14 @@ static void FLASH_SetErrorCode(void) flags |= FLASH_FLAG_OPTVERRUSR; } #endif /* FLASH_SR_OPTVERRUSR */ - + if(__HAL_FLASH_GET_FLAG(FLASH_FLAG_SIZERR)) + { + pFlash.ErrorCode |= HAL_FLASH_ERROR_SIZE; + flags |= FLASH_FLAG_SIZERR; + } /* Clear FLASH error pending bits */ __HAL_FLASH_CLEAR_FLAG(flags); -} +} /** * @} */ diff --git a/cubemx/Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_gpio.c b/cubemx/Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_gpio.c index 1dbe14f..5f77060 100644 --- a/cubemx/Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_gpio.c +++ b/cubemx/Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_gpio.c @@ -133,14 +133,6 @@ /** @addtogroup GPIO_Private_Constants * @{ */ -#define GPIO_MODE (0x00000003U) -#define EXTI_MODE (0x10000000U) -#define GPIO_MODE_IT (0x00010000U) -#define GPIO_MODE_EVT (0x00020000U) -#define RISING_EDGE (0x00100000U) -#define FALLING_EDGE (0x00200000U) -#define GPIO_OUTPUT_TYPE (0x00000010U) - #define GPIO_NUMBER (16U) /** @@ -185,7 +177,6 @@ void HAL_GPIO_Init(GPIO_TypeDef *GPIOx, GPIO_InitTypeDef *GPIO_Init) assert_param(IS_GPIO_ALL_INSTANCE(GPIOx)); assert_param(IS_GPIO_PIN(GPIO_Init->Pin)); assert_param(IS_GPIO_MODE(GPIO_Init->Mode)); - assert_param(IS_GPIO_PULL(GPIO_Init->Pull)); /* Configure the port pins */ while (((GPIO_Init->Pin) >> position) != 0) @@ -197,8 +188,8 @@ void HAL_GPIO_Init(GPIO_TypeDef *GPIOx, GPIO_InitTypeDef *GPIO_Init) { /*--------------------- GPIO Mode Configuration ------------------------*/ /* In case of Output or Alternate function mode selection */ - if ((GPIO_Init->Mode == GPIO_MODE_OUTPUT_PP) || (GPIO_Init->Mode == GPIO_MODE_AF_PP) || - (GPIO_Init->Mode == GPIO_MODE_OUTPUT_OD) || (GPIO_Init->Mode == GPIO_MODE_AF_OD)) + if (((GPIO_Init->Mode & GPIO_MODE) == MODE_OUTPUT) || + ((GPIO_Init->Mode & GPIO_MODE) == MODE_AF)) { /* Check the Speed parameter */ assert_param(IS_GPIO_SPEED(GPIO_Init->Speed)); @@ -211,18 +202,24 @@ void HAL_GPIO_Init(GPIO_TypeDef *GPIOx, GPIO_InitTypeDef *GPIO_Init) /* Configure the IO Output Type */ temp = GPIOx->OTYPER; CLEAR_BIT(temp, GPIO_OTYPER_OT_0 << position) ; - SET_BIT(temp, ((GPIO_Init->Mode & GPIO_OUTPUT_TYPE) >> 4) << position); + SET_BIT(temp, ((GPIO_Init->Mode & OUTPUT_TYPE) >> OUTPUT_TYPE_Pos) << position); GPIOx->OTYPER = temp; } - /* Activate the Pull-up or Pull down resistor for the current IO */ - temp = GPIOx->PUPDR; - CLEAR_BIT(temp, GPIO_PUPDR_PUPDR0 << (position * 2)); - SET_BIT(temp, (GPIO_Init->Pull) << (position * 2)); - GPIOx->PUPDR = temp; + if ((GPIO_Init->Mode & GPIO_MODE) != MODE_ANALOG) + { + /* Check the Pull parameter */ + assert_param(IS_GPIO_PULL(GPIO_Init->Pull)); + + /* Activate the Pull-up or Pull down resistor for the current IO */ + temp = GPIOx->PUPDR; + CLEAR_BIT(temp, GPIO_PUPDR_PUPDR0 << (position * 2)); + SET_BIT(temp, (GPIO_Init->Pull) << (position * 2)); + GPIOx->PUPDR = temp; + } /* In case of Alternate function mode selection */ - if ((GPIO_Init->Mode == GPIO_MODE_AF_PP) || (GPIO_Init->Mode == GPIO_MODE_AF_OD)) + if ((GPIO_Init->Mode & GPIO_MODE) == MODE_AF) { /* Check the Alternate function parameters */ assert_param(IS_GPIO_AF_INSTANCE(GPIOx)); @@ -244,7 +241,7 @@ void HAL_GPIO_Init(GPIO_TypeDef *GPIOx, GPIO_InitTypeDef *GPIO_Init) /*--------------------- EXTI Mode Configuration ------------------------*/ /* Configure the External Interrupt or event for the current IO */ - if ((GPIO_Init->Mode & EXTI_MODE) == EXTI_MODE) + if ((GPIO_Init->Mode & EXTI_MODE) != 0x00U) { /* Enable SYSCFG Clock */ __HAL_RCC_SYSCFG_CLK_ENABLE(); @@ -257,7 +254,7 @@ void HAL_GPIO_Init(GPIO_TypeDef *GPIOx, GPIO_InitTypeDef *GPIO_Init) /* Clear EXTI line configuration */ temp = EXTI->IMR; CLEAR_BIT(temp, (uint32_t)iocurrent); - if ((GPIO_Init->Mode & GPIO_MODE_IT) == GPIO_MODE_IT) + if ((GPIO_Init->Mode & EXTI_IT) != 0x00U) { SET_BIT(temp, iocurrent); } @@ -265,7 +262,7 @@ void HAL_GPIO_Init(GPIO_TypeDef *GPIOx, GPIO_InitTypeDef *GPIO_Init) temp = EXTI->EMR; CLEAR_BIT(temp, (uint32_t)iocurrent); - if ((GPIO_Init->Mode & GPIO_MODE_EVT) == GPIO_MODE_EVT) + if ((GPIO_Init->Mode & EXTI_EVT) != 0x00U) { SET_BIT(temp, iocurrent); } @@ -274,7 +271,7 @@ void HAL_GPIO_Init(GPIO_TypeDef *GPIOx, GPIO_InitTypeDef *GPIO_Init) /* Clear Rising Falling edge configuration */ temp = EXTI->RTSR; CLEAR_BIT(temp, (uint32_t)iocurrent); - if ((GPIO_Init->Mode & RISING_EDGE) == RISING_EDGE) + if ((GPIO_Init->Mode & TRIGGER_RISING) != 0x00U) { SET_BIT(temp, iocurrent); } @@ -282,7 +279,7 @@ void HAL_GPIO_Init(GPIO_TypeDef *GPIOx, GPIO_InitTypeDef *GPIO_Init) temp = EXTI->FTSR; CLEAR_BIT(temp, (uint32_t)iocurrent); - if ((GPIO_Init->Mode & FALLING_EDGE) == FALLING_EDGE) + if ((GPIO_Init->Mode & TRIGGER_FALLING) != 0x00U) { SET_BIT(temp, iocurrent); } diff --git a/cubemx/Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_rcc_ex.c b/cubemx/Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_rcc_ex.c index 6dac309..b6cfd0c 100644 --- a/cubemx/Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_rcc_ex.c +++ b/cubemx/Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_rcc_ex.c @@ -200,7 +200,17 @@ HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClk } } } - __HAL_RCC_RTC_CONFIG(PeriphClkInit->RTCClockSelection); +#if defined(LCD) + if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_LCD) == RCC_PERIPHCLK_LCD) + { + __HAL_RCC_LCD_CONFIG(PeriphClkInit->LCDClockSelection); + } +#endif /* LCD */ + + if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_RTC) == RCC_PERIPHCLK_RTC) + { + __HAL_RCC_RTC_CONFIG(PeriphClkInit->RTCClockSelection); + } /* Require to disable power clock if necessary */ if(pwrclkchanged == SET) diff --git a/cubemx/Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_spi.c b/cubemx/Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_spi.c index a91c885..f457691 100644 --- a/cubemx/Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_spi.c +++ b/cubemx/Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_spi.c @@ -942,6 +942,9 @@ error: */ HAL_StatusTypeDef HAL_SPI_Receive(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size, uint32_t Timeout) { +#if (USE_SPI_CRC != 0U) + __IO uint32_t tmpreg = 0U; +#endif /* USE_SPI_CRC */ uint32_t tickstart; HAL_StatusTypeDef errorcode = HAL_OK; @@ -1093,7 +1096,9 @@ HAL_StatusTypeDef HAL_SPI_Receive(SPI_HandleTypeDef *hspi, uint8_t *pData, uint1 } /* Read CRC to Flush DR and RXNE flag */ - READ_REG(hspi->Instance->DR); + tmpreg = READ_REG(hspi->Instance->DR); + /* To avoid GCC warning */ + UNUSED(tmpreg); } #endif /* USE_SPI_CRC */ @@ -1140,6 +1145,9 @@ HAL_StatusTypeDef HAL_SPI_TransmitReceive(SPI_HandleTypeDef *hspi, uint8_t *pTxD uint32_t tmp_mode; HAL_SPI_StateTypeDef tmp_state; uint32_t tickstart; +#if (USE_SPI_CRC != 0U) + __IO uint32_t tmpreg = 0U; +#endif /* USE_SPI_CRC */ /* Variable used to alternate Rx and Tx during transfer */ uint32_t txallowed = 1U; @@ -1310,7 +1318,9 @@ HAL_StatusTypeDef HAL_SPI_TransmitReceive(SPI_HandleTypeDef *hspi, uint8_t *pTxD goto error; } /* Read CRC */ - READ_REG(hspi->Instance->DR); + tmpreg = READ_REG(hspi->Instance->DR); + /* To avoid GCC warning */ + UNUSED(tmpreg); } /* Check if CRC error occurred */ @@ -2739,6 +2749,9 @@ static void SPI_DMAReceiveCplt(DMA_HandleTypeDef *hdma) { SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); /* Derogation MISRAC2012-Rule-11.5 */ uint32_t tickstart; +#if (USE_SPI_CRC != 0U) + __IO uint32_t tmpreg = 0U; +#endif /* USE_SPI_CRC */ /* Init tickstart for timeout management*/ tickstart = HAL_GetTick(); @@ -2760,7 +2773,9 @@ static void SPI_DMAReceiveCplt(DMA_HandleTypeDef *hdma) SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC); } /* Read CRC */ - READ_REG(hspi->Instance->DR); + tmpreg = READ_REG(hspi->Instance->DR); + /* To avoid GCC warning */ + UNUSED(tmpreg); } #endif /* USE_SPI_CRC */ @@ -2823,6 +2838,9 @@ static void SPI_DMATransmitReceiveCplt(DMA_HandleTypeDef *hdma) { SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); /* Derogation MISRAC2012-Rule-11.5 */ uint32_t tickstart; +#if (USE_SPI_CRC != 0U) + __IO uint32_t tmpreg = 0U; +#endif /* USE_SPI_CRC */ /* Init tickstart for timeout management*/ tickstart = HAL_GetTick(); @@ -2843,7 +2861,9 @@ static void SPI_DMATransmitReceiveCplt(DMA_HandleTypeDef *hdma) SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC); } /* Read CRC to Flush DR and RXNE flag */ - READ_REG(hspi->Instance->DR); + tmpreg = READ_REG(hspi->Instance->DR); + /* To avoid GCC warning */ + UNUSED(tmpreg); } #endif /* USE_SPI_CRC */ @@ -3158,8 +3178,15 @@ static void SPI_2linesRxISR_8BIT(struct __SPI_HandleTypeDef *hspi) */ static void SPI_2linesRxISR_8BITCRC(struct __SPI_HandleTypeDef *hspi) { + __IO uint8_t * ptmpreg8; + __IO uint8_t tmpreg8 = 0; + + /* Initialize the 8bit temporary pointer */ + ptmpreg8 = (__IO uint8_t *)&hspi->Instance->DR; /* Read 8bit CRC to flush Data Register */ - READ_REG(*(__IO uint8_t *)&hspi->Instance->DR); + tmpreg8 = *ptmpreg8; + /* To avoid GCC warning */ + UNUSED(tmpreg8); /* Disable RXNE and ERR interrupt */ __HAL_SPI_DISABLE_IT(hspi, (SPI_IT_RXNE | SPI_IT_ERR)); @@ -3249,8 +3276,12 @@ static void SPI_2linesRxISR_16BIT(struct __SPI_HandleTypeDef *hspi) */ static void SPI_2linesRxISR_16BITCRC(struct __SPI_HandleTypeDef *hspi) { + __IO uint32_t tmpreg = 0U; + /* Read 16bit CRC to flush Data Register */ - READ_REG(hspi->Instance->DR); + tmpreg = READ_REG(hspi->Instance->DR); + /* To avoid GCC warning */ + UNUSED(tmpreg); /* Disable RXNE interrupt */ __HAL_SPI_DISABLE_IT(hspi, SPI_IT_RXNE); @@ -3305,8 +3336,15 @@ static void SPI_2linesTxISR_16BIT(struct __SPI_HandleTypeDef *hspi) */ static void SPI_RxISR_8BITCRC(struct __SPI_HandleTypeDef *hspi) { + __IO uint8_t * ptmpreg8; + __IO uint8_t tmpreg8 = 0; + + /* Initialize the 8bit temporary pointer */ + ptmpreg8 = (__IO uint8_t *)&hspi->Instance->DR; /* Read 8bit CRC to flush Data Register */ - READ_REG(*(__IO uint8_t *)&hspi->Instance->DR); + tmpreg8 = *ptmpreg8; + /* To avoid GCC warning */ + UNUSED(tmpreg8); SPI_CloseRx_ISR(hspi); } @@ -3354,8 +3392,12 @@ static void SPI_RxISR_8BIT(struct __SPI_HandleTypeDef *hspi) */ static void SPI_RxISR_16BITCRC(struct __SPI_HandleTypeDef *hspi) { + __IO uint32_t tmpreg = 0U; + /* Read 16bit CRC to flush Data Register */ - READ_REG(hspi->Instance->DR); + tmpreg = READ_REG(hspi->Instance->DR); + /* To avoid GCC warning */ + UNUSED(tmpreg); /* Disable RXNE and ERR interrupt */ __HAL_SPI_DISABLE_IT(hspi, (SPI_IT_RXNE | SPI_IT_ERR)); @@ -3836,6 +3878,7 @@ static void SPI_CloseTx_ISR(SPI_HandleTypeDef *hspi) */ static void SPI_AbortRx_ISR(SPI_HandleTypeDef *hspi) { + __IO uint32_t tmpreg = 0U; __IO uint32_t count = SPI_DEFAULT_TIMEOUT * (SystemCoreClock / 24U / 1000U); /* Wait until TXE flag is set */ @@ -3855,8 +3898,10 @@ static void SPI_AbortRx_ISR(SPI_HandleTypeDef *hspi) /* Disable TXEIE, RXNEIE and ERRIE(mode fault event, overrun error, TI frame error) interrupts */ CLEAR_BIT(hspi->Instance->CR2, (SPI_CR2_TXEIE | SPI_CR2_RXNEIE | SPI_CR2_ERRIE)); - /* Read CRC to flush Data Register */ - READ_REG(hspi->Instance->DR); + /* Flush Data Register by a blank read */ + tmpreg = READ_REG(hspi->Instance->DR); + /* To avoid GCC warning */ + UNUSED(tmpreg); hspi->State = HAL_SPI_STATE_ABORT; } diff --git a/cubemx/Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_tim.c b/cubemx/Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_tim.c index 822c6b0..80b60a4 100644 --- a/cubemx/Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_tim.c +++ b/cubemx/Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_tim.c @@ -220,6 +220,8 @@ static void TIM_ETR_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ExtTRGPrescaler, static void TIM_CCxChannelCmd(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ChannelState); static void TIM_DMAPeriodElapsedCplt(DMA_HandleTypeDef *hdma); static void TIM_DMAPeriodElapsedHalfCplt(DMA_HandleTypeDef *hdma); +static void TIM_DMADelayPulseCplt(DMA_HandleTypeDef *hdma); +static void TIM_DMADelayPulseHalfCplt(DMA_HandleTypeDef *hdma); static void TIM_DMATriggerCplt(DMA_HandleTypeDef *hdma); static void TIM_DMATriggerHalfCplt(DMA_HandleTypeDef *hdma); static HAL_StatusTypeDef TIM_SlaveTimer_SetConfig(TIM_HandleTypeDef *htim, @@ -500,7 +502,7 @@ HAL_StatusTypeDef HAL_TIM_Base_Stop_IT(TIM_HandleTypeDef *htim) { /* Check the parameters */ assert_param(IS_TIM_INSTANCE(htim->Instance)); - + /* Disable the TIM Update interrupt */ __HAL_TIM_DISABLE_IT(htim, TIM_IT_UPDATE); @@ -557,8 +559,10 @@ HAL_StatusTypeDef HAL_TIM_Base_Start_DMA(TIM_HandleTypeDef *htim, uint32_t *pDat htim->hdma[TIM_DMA_ID_UPDATE]->XferErrorCallback = TIM_DMAError ; /* Enable the DMA channel */ - if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_UPDATE], (uint32_t)pData, (uint32_t)&htim->Instance->ARR, Length) != HAL_OK) + if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_UPDATE], (uint32_t)pData, (uint32_t)&htim->Instance->ARR, + Length) != HAL_OK) { + /* Return error status */ return HAL_ERROR; } @@ -1043,8 +1047,10 @@ HAL_StatusTypeDef HAL_TIM_OC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ; /* Enable the DMA channel */ - if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)pData, (uint32_t)&htim->Instance->CCR1, Length) != HAL_OK) + if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)pData, (uint32_t)&htim->Instance->CCR1, + Length) != HAL_OK) { + /* Return error status */ return HAL_ERROR; } @@ -1063,8 +1069,10 @@ HAL_StatusTypeDef HAL_TIM_OC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ; /* Enable the DMA channel */ - if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)pData, (uint32_t)&htim->Instance->CCR2, Length) != HAL_OK) + if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)pData, (uint32_t)&htim->Instance->CCR2, + Length) != HAL_OK) { + /* Return error status */ return HAL_ERROR; } @@ -1083,8 +1091,10 @@ HAL_StatusTypeDef HAL_TIM_OC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError ; /* Enable the DMA channel */ - if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)pData, (uint32_t)&htim->Instance->CCR3, Length) != HAL_OK) + if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)pData, (uint32_t)&htim->Instance->CCR3, + Length) != HAL_OK) { + /* Return error status */ return HAL_ERROR; } /* Enable the TIM Capture/Compare 3 DMA request */ @@ -1102,8 +1112,10 @@ HAL_StatusTypeDef HAL_TIM_OC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = TIM_DMAError ; /* Enable the DMA channel */ - if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)pData, (uint32_t)&htim->Instance->CCR4, Length) != HAL_OK) + if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)pData, (uint32_t)&htim->Instance->CCR4, + Length) != HAL_OK) { + /* Return error status */ return HAL_ERROR; } /* Enable the TIM Capture/Compare 4 DMA request */ @@ -1637,8 +1649,10 @@ HAL_StatusTypeDef HAL_TIM_PWM_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channe htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ; /* Enable the DMA channel */ - if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)pData, (uint32_t)&htim->Instance->CCR1, Length) != HAL_OK) + if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)pData, (uint32_t)&htim->Instance->CCR1, + Length) != HAL_OK) { + /* Return error status */ return HAL_ERROR; } @@ -1657,8 +1671,10 @@ HAL_StatusTypeDef HAL_TIM_PWM_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channe htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ; /* Enable the DMA channel */ - if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)pData, (uint32_t)&htim->Instance->CCR2, Length) != HAL_OK) + if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)pData, (uint32_t)&htim->Instance->CCR2, + Length) != HAL_OK) { + /* Return error status */ return HAL_ERROR; } /* Enable the TIM Capture/Compare 2 DMA request */ @@ -1676,8 +1692,10 @@ HAL_StatusTypeDef HAL_TIM_PWM_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channe htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError ; /* Enable the DMA channel */ - if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)pData, (uint32_t)&htim->Instance->CCR3, Length) != HAL_OK) + if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)pData, (uint32_t)&htim->Instance->CCR3, + Length) != HAL_OK) { + /* Return error status */ return HAL_ERROR; } /* Enable the TIM Output Capture/Compare 3 request */ @@ -1695,8 +1713,10 @@ HAL_StatusTypeDef HAL_TIM_PWM_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channe htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = TIM_DMAError ; /* Enable the DMA channel */ - if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)pData, (uint32_t)&htim->Instance->CCR4, Length) != HAL_OK) + if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)pData, (uint32_t)&htim->Instance->CCR4, + Length) != HAL_OK) { + /* Return error status */ return HAL_ERROR; } /* Enable the TIM Capture/Compare 4 DMA request */ @@ -2222,6 +2242,23 @@ HAL_StatusTypeDef HAL_TIM_IC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel return HAL_ERROR; } + /* Enable the Input Capture channel */ + TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE); + + /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */ + if (IS_TIM_SLAVE_INSTANCE(htim->Instance)) + { + tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; + if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) + { + __HAL_TIM_ENABLE(htim); + } + } + else + { + __HAL_TIM_ENABLE(htim); + } + switch (Channel) { case TIM_CHANNEL_1: @@ -2234,8 +2271,10 @@ HAL_StatusTypeDef HAL_TIM_IC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ; /* Enable the DMA channel */ - if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->CCR1, (uint32_t)pData, Length) != HAL_OK) + if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->CCR1, (uint32_t)pData, + Length) != HAL_OK) { + /* Return error status */ return HAL_ERROR; } /* Enable the TIM Capture/Compare 1 DMA request */ @@ -2253,8 +2292,10 @@ HAL_StatusTypeDef HAL_TIM_IC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ; /* Enable the DMA channel */ - if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)&htim->Instance->CCR2, (uint32_t)pData, Length) != HAL_OK) + if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)&htim->Instance->CCR2, (uint32_t)pData, + Length) != HAL_OK) { + /* Return error status */ return HAL_ERROR; } /* Enable the TIM Capture/Compare 2 DMA request */ @@ -2272,8 +2313,10 @@ HAL_StatusTypeDef HAL_TIM_IC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError ; /* Enable the DMA channel */ - if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)&htim->Instance->CCR3, (uint32_t)pData, Length) != HAL_OK) + if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)&htim->Instance->CCR3, (uint32_t)pData, + Length) != HAL_OK) { + /* Return error status */ return HAL_ERROR; } /* Enable the TIM Capture/Compare 3 DMA request */ @@ -2291,8 +2334,10 @@ HAL_StatusTypeDef HAL_TIM_IC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = TIM_DMAError ; /* Enable the DMA channel */ - if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)&htim->Instance->CCR4, (uint32_t)pData, Length) != HAL_OK) + if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)&htim->Instance->CCR4, (uint32_t)pData, + Length) != HAL_OK) { + /* Return error status */ return HAL_ERROR; } /* Enable the TIM Capture/Compare 4 DMA request */ @@ -2304,23 +2349,6 @@ HAL_StatusTypeDef HAL_TIM_IC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel break; } - /* Enable the Input Capture channel */ - TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE); - - /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */ - if (IS_TIM_SLAVE_INSTANCE(htim->Instance)) - { - tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; - if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) - { - __HAL_TIM_ENABLE(htim); - } - } - else - { - __HAL_TIM_ENABLE(htim); - } - /* Return function status */ return HAL_OK; } @@ -2570,11 +2598,12 @@ __weak void HAL_TIM_OnePulse_MspDeInit(TIM_HandleTypeDef *htim) /** * @brief Starts the TIM One Pulse signal generation. + * @note Though OutputChannel parameter is deprecated and ignored by the function + * it has been kept to avoid HAL_TIM API compatibility break. + * @note The pulse output channel is determined when calling + * @ref HAL_TIM_OnePulse_ConfigChannel(). * @param htim TIM One Pulse handle - * @param OutputChannel TIM Channels to be enabled - * This parameter can be one of the following values: - * @arg TIM_CHANNEL_1: TIM Channel 1 selected - * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @param OutputChannel See note above * @retval HAL status */ HAL_StatusTypeDef HAL_TIM_OnePulse_Start(TIM_HandleTypeDef *htim, uint32_t OutputChannel) @@ -2587,7 +2616,7 @@ HAL_StatusTypeDef HAL_TIM_OnePulse_Start(TIM_HandleTypeDef *htim, uint32_t Outpu /* Check the TIM channels state */ if ((channel_1_state != HAL_TIM_CHANNEL_STATE_READY) - || (channel_2_state != HAL_TIM_CHANNEL_STATE_READY)) + || (channel_2_state != HAL_TIM_CHANNEL_STATE_READY)) { return HAL_ERROR; } @@ -2600,7 +2629,7 @@ HAL_StatusTypeDef HAL_TIM_OnePulse_Start(TIM_HandleTypeDef *htim, uint32_t Outpu (in the OPM Mode the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2) if TIM_CHANNEL_1 is used as output, the TIM_CHANNEL_2 will be used as input and if TIM_CHANNEL_1 is used as input, the TIM_CHANNEL_2 will be used as output - in all combinations, the TIM_CHANNEL_1 and TIM_CHANNEL_2 should be enabled together + whatever the combination, the TIM_CHANNEL_1 and TIM_CHANNEL_2 should be enabled together No need to enable the counter, it's enabled automatically by hardware (the counter starts in response to a stimulus and generate a pulse */ @@ -2614,11 +2643,12 @@ HAL_StatusTypeDef HAL_TIM_OnePulse_Start(TIM_HandleTypeDef *htim, uint32_t Outpu /** * @brief Stops the TIM One Pulse signal generation. + * @note Though OutputChannel parameter is deprecated and ignored by the function + * it has been kept to avoid HAL_TIM API compatibility break. + * @note The pulse output channel is determined when calling + * @ref HAL_TIM_OnePulse_ConfigChannel(). * @param htim TIM One Pulse handle - * @param OutputChannel TIM Channels to be disable - * This parameter can be one of the following values: - * @arg TIM_CHANNEL_1: TIM Channel 1 selected - * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @param OutputChannel See note above * @retval HAL status */ HAL_StatusTypeDef HAL_TIM_OnePulse_Stop(TIM_HandleTypeDef *htim, uint32_t OutputChannel) @@ -2630,7 +2660,7 @@ HAL_StatusTypeDef HAL_TIM_OnePulse_Stop(TIM_HandleTypeDef *htim, uint32_t Output (in the OPM Mode the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2) if TIM_CHANNEL_1 is used as output, the TIM_CHANNEL_2 will be used as input and if TIM_CHANNEL_1 is used as input, the TIM_CHANNEL_2 will be used as output - in all combinations, the TIM_CHANNEL_1 and TIM_CHANNEL_2 should be disabled together */ + whatever the combination, the TIM_CHANNEL_1 and TIM_CHANNEL_2 should be disabled together */ TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE); TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE); @@ -2648,11 +2678,12 @@ HAL_StatusTypeDef HAL_TIM_OnePulse_Stop(TIM_HandleTypeDef *htim, uint32_t Output /** * @brief Starts the TIM One Pulse signal generation in interrupt mode. + * @note Though OutputChannel parameter is deprecated and ignored by the function + * it has been kept to avoid HAL_TIM API compatibility break. + * @note The pulse output channel is determined when calling + * @ref HAL_TIM_OnePulse_ConfigChannel(). * @param htim TIM One Pulse handle - * @param OutputChannel TIM Channels to be enabled - * This parameter can be one of the following values: - * @arg TIM_CHANNEL_1: TIM Channel 1 selected - * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @param OutputChannel See note above * @retval HAL status */ HAL_StatusTypeDef HAL_TIM_OnePulse_Start_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel) @@ -2665,7 +2696,7 @@ HAL_StatusTypeDef HAL_TIM_OnePulse_Start_IT(TIM_HandleTypeDef *htim, uint32_t Ou /* Check the TIM channels state */ if ((channel_1_state != HAL_TIM_CHANNEL_STATE_READY) - || (channel_2_state != HAL_TIM_CHANNEL_STATE_READY)) + || (channel_2_state != HAL_TIM_CHANNEL_STATE_READY)) { return HAL_ERROR; } @@ -2678,7 +2709,7 @@ HAL_StatusTypeDef HAL_TIM_OnePulse_Start_IT(TIM_HandleTypeDef *htim, uint32_t Ou (in the OPM Mode the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2) if TIM_CHANNEL_1 is used as output, the TIM_CHANNEL_2 will be used as input and if TIM_CHANNEL_1 is used as input, the TIM_CHANNEL_2 will be used as output - in all combinations, the TIM_CHANNEL_1 and TIM_CHANNEL_2 should be enabled together + whatever the combination, the TIM_CHANNEL_1 and TIM_CHANNEL_2 should be enabled together No need to enable the counter, it's enabled automatically by hardware (the counter starts in response to a stimulus and generate a pulse */ @@ -2698,11 +2729,12 @@ HAL_StatusTypeDef HAL_TIM_OnePulse_Start_IT(TIM_HandleTypeDef *htim, uint32_t Ou /** * @brief Stops the TIM One Pulse signal generation in interrupt mode. + * @note Though OutputChannel parameter is deprecated and ignored by the function + * it has been kept to avoid HAL_TIM API compatibility break. + * @note The pulse output channel is determined when calling + * @ref HAL_TIM_OnePulse_ConfigChannel(). * @param htim TIM One Pulse handle - * @param OutputChannel TIM Channels to be enabled - * This parameter can be one of the following values: - * @arg TIM_CHANNEL_1: TIM Channel 1 selected - * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @param OutputChannel See note above * @retval HAL status */ HAL_StatusTypeDef HAL_TIM_OnePulse_Stop_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel) @@ -2720,7 +2752,7 @@ HAL_StatusTypeDef HAL_TIM_OnePulse_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Out (in the OPM Mode the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2) if TIM_CHANNEL_1 is used as output, the TIM_CHANNEL_2 will be used as input and if TIM_CHANNEL_1 is used as input, the TIM_CHANNEL_2 will be used as output - in all combinations, the TIM_CHANNEL_1 and TIM_CHANNEL_2 should be disabled together */ + whatever the combination, the TIM_CHANNEL_1 and TIM_CHANNEL_2 should be disabled together */ TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE); TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE); @@ -3000,7 +3032,7 @@ HAL_StatusTypeDef HAL_TIM_Encoder_Start(TIM_HandleTypeDef *htim, uint32_t Channe else { if ((channel_1_state != HAL_TIM_CHANNEL_STATE_READY) - || (channel_2_state != HAL_TIM_CHANNEL_STATE_READY)) + || (channel_2_state != HAL_TIM_CHANNEL_STATE_READY)) { return HAL_ERROR; } @@ -3087,7 +3119,7 @@ HAL_StatusTypeDef HAL_TIM_Encoder_Stop(TIM_HandleTypeDef *htim, uint32_t Channel { TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY); } - else + else { TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY); @@ -3141,7 +3173,7 @@ HAL_StatusTypeDef HAL_TIM_Encoder_Start_IT(TIM_HandleTypeDef *htim, uint32_t Cha else { if ((channel_1_state != HAL_TIM_CHANNEL_STATE_READY) - || (channel_2_state != HAL_TIM_CHANNEL_STATE_READY)) + || (channel_2_state != HAL_TIM_CHANNEL_STATE_READY)) { return HAL_ERROR; } @@ -3236,7 +3268,7 @@ HAL_StatusTypeDef HAL_TIM_Encoder_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Chan { TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY); } - else + else { TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY); @@ -3316,12 +3348,12 @@ HAL_StatusTypeDef HAL_TIM_Encoder_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Ch else { if ((channel_1_state == HAL_TIM_CHANNEL_STATE_BUSY) - || (channel_2_state == HAL_TIM_CHANNEL_STATE_BUSY)) + || (channel_2_state == HAL_TIM_CHANNEL_STATE_BUSY)) { return HAL_BUSY; } else if ((channel_1_state == HAL_TIM_CHANNEL_STATE_READY) - && (channel_2_state == HAL_TIM_CHANNEL_STATE_READY)) + && (channel_2_state == HAL_TIM_CHANNEL_STATE_READY)) { if ((((pData1 == NULL) || (pData2 == NULL))) && (Length > 0U)) { @@ -3351,8 +3383,10 @@ HAL_StatusTypeDef HAL_TIM_Encoder_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Ch htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ; /* Enable the DMA channel */ - if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->CCR1, (uint32_t)pData1, Length) != HAL_OK) + if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->CCR1, (uint32_t)pData1, + Length) != HAL_OK) { + /* Return error status */ return HAL_ERROR; } /* Enable the TIM Input Capture DMA request */ @@ -3375,8 +3409,10 @@ HAL_StatusTypeDef HAL_TIM_Encoder_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Ch /* Set the DMA error callback */ htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError; /* Enable the DMA channel */ - if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)&htim->Instance->CCR2, (uint32_t)pData2, Length) != HAL_OK) + if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)&htim->Instance->CCR2, (uint32_t)pData2, + Length) != HAL_OK) { + /* Return error status */ return HAL_ERROR; } /* Enable the TIM Input Capture DMA request */ @@ -3400,8 +3436,10 @@ HAL_StatusTypeDef HAL_TIM_Encoder_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Ch htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ; /* Enable the DMA channel */ - if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->CCR1, (uint32_t)pData1, Length) != HAL_OK) + if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->CCR1, (uint32_t)pData1, + Length) != HAL_OK) { + /* Return error status */ return HAL_ERROR; } @@ -3413,8 +3451,10 @@ HAL_StatusTypeDef HAL_TIM_Encoder_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Ch htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ; /* Enable the DMA channel */ - if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)&htim->Instance->CCR2, (uint32_t)pData2, Length) != HAL_OK) + if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)&htim->Instance->CCR2, (uint32_t)pData2, + Length) != HAL_OK) { + /* Return error status */ return HAL_ERROR; } /* Enable the Peripheral */ @@ -3492,7 +3532,7 @@ HAL_StatusTypeDef HAL_TIM_Encoder_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Cha { TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY); } - else + else { TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY); @@ -4212,8 +4252,9 @@ HAL_StatusTypeDef HAL_TIM_DMABurst_MultiWriteStart(TIM_HandleTypeDef *htim, uint /* Enable the DMA channel */ if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_UPDATE], (uint32_t)BurstBuffer, - (uint32_t)&htim->Instance->DMAR, DataLength) != HAL_OK) + (uint32_t)&htim->Instance->DMAR, DataLength) != HAL_OK) { + /* Return error status */ return HAL_ERROR; } break; @@ -4229,8 +4270,9 @@ HAL_StatusTypeDef HAL_TIM_DMABurst_MultiWriteStart(TIM_HandleTypeDef *htim, uint /* Enable the DMA channel */ if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)BurstBuffer, - (uint32_t)&htim->Instance->DMAR, DataLength) != HAL_OK) + (uint32_t)&htim->Instance->DMAR, DataLength) != HAL_OK) { + /* Return error status */ return HAL_ERROR; } break; @@ -4246,8 +4288,9 @@ HAL_StatusTypeDef HAL_TIM_DMABurst_MultiWriteStart(TIM_HandleTypeDef *htim, uint /* Enable the DMA channel */ if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)BurstBuffer, - (uint32_t)&htim->Instance->DMAR, DataLength) != HAL_OK) + (uint32_t)&htim->Instance->DMAR, DataLength) != HAL_OK) { + /* Return error status */ return HAL_ERROR; } break; @@ -4263,8 +4306,9 @@ HAL_StatusTypeDef HAL_TIM_DMABurst_MultiWriteStart(TIM_HandleTypeDef *htim, uint /* Enable the DMA channel */ if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)BurstBuffer, - (uint32_t)&htim->Instance->DMAR, DataLength) != HAL_OK) + (uint32_t)&htim->Instance->DMAR, DataLength) != HAL_OK) { + /* Return error status */ return HAL_ERROR; } break; @@ -4280,8 +4324,9 @@ HAL_StatusTypeDef HAL_TIM_DMABurst_MultiWriteStart(TIM_HandleTypeDef *htim, uint /* Enable the DMA channel */ if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)BurstBuffer, - (uint32_t)&htim->Instance->DMAR, DataLength) != HAL_OK) + (uint32_t)&htim->Instance->DMAR, DataLength) != HAL_OK) { + /* Return error status */ return HAL_ERROR; } break; @@ -4297,8 +4342,9 @@ HAL_StatusTypeDef HAL_TIM_DMABurst_MultiWriteStart(TIM_HandleTypeDef *htim, uint /* Enable the DMA channel */ if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_TRIGGER], (uint32_t)BurstBuffer, - (uint32_t)&htim->Instance->DMAR, DataLength) != HAL_OK) + (uint32_t)&htim->Instance->DMAR, DataLength) != HAL_OK) { + /* Return error status */ return HAL_ERROR; } break; @@ -4324,7 +4370,6 @@ HAL_StatusTypeDef HAL_TIM_DMABurst_MultiWriteStart(TIM_HandleTypeDef *htim, uint */ HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStop(TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc) { - HAL_StatusTypeDef status = HAL_OK; /* Check the parameters */ assert_param(IS_TIM_DMA_SOURCE(BurstRequestSrc)); @@ -4348,7 +4393,7 @@ HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStop(TIM_HandleTypeDef *htim, uint32_t B } case TIM_DMA_CC3: { - status = HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC3]); + (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC3]); break; } case TIM_DMA_CC4: @@ -4365,17 +4410,14 @@ HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStop(TIM_HandleTypeDef *htim, uint32_t B break; } - if (HAL_OK == status) - { - /* Disable the TIM Update DMA request */ - __HAL_TIM_DISABLE_DMA(htim, BurstRequestSrc); - } + /* Disable the TIM Update DMA request */ + __HAL_TIM_DISABLE_DMA(htim, BurstRequestSrc); /* Change the DMA burst operation state */ htim->DMABurstState = HAL_DMA_BURST_STATE_READY; /* Return function status */ - return status; + return HAL_OK; } /** @@ -4501,8 +4543,9 @@ HAL_StatusTypeDef HAL_TIM_DMABurst_MultiReadStart(TIM_HandleTypeDef *htim, uint3 /* Enable the DMA channel */ if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_UPDATE], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, - DataLength) != HAL_OK) + DataLength) != HAL_OK) { + /* Return error status */ return HAL_ERROR; } break; @@ -4518,8 +4561,9 @@ HAL_StatusTypeDef HAL_TIM_DMABurst_MultiReadStart(TIM_HandleTypeDef *htim, uint3 /* Enable the DMA channel */ if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, - DataLength) != HAL_OK) + DataLength) != HAL_OK) { + /* Return error status */ return HAL_ERROR; } break; @@ -4535,8 +4579,9 @@ HAL_StatusTypeDef HAL_TIM_DMABurst_MultiReadStart(TIM_HandleTypeDef *htim, uint3 /* Enable the DMA channel */ if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, - DataLength) != HAL_OK) + DataLength) != HAL_OK) { + /* Return error status */ return HAL_ERROR; } break; @@ -4552,8 +4597,9 @@ HAL_StatusTypeDef HAL_TIM_DMABurst_MultiReadStart(TIM_HandleTypeDef *htim, uint3 /* Enable the DMA channel */ if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, - DataLength) != HAL_OK) + DataLength) != HAL_OK) { + /* Return error status */ return HAL_ERROR; } break; @@ -4569,8 +4615,9 @@ HAL_StatusTypeDef HAL_TIM_DMABurst_MultiReadStart(TIM_HandleTypeDef *htim, uint3 /* Enable the DMA channel */ if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, - DataLength) != HAL_OK) + DataLength) != HAL_OK) { + /* Return error status */ return HAL_ERROR; } break; @@ -4586,8 +4633,9 @@ HAL_StatusTypeDef HAL_TIM_DMABurst_MultiReadStart(TIM_HandleTypeDef *htim, uint3 /* Enable the DMA channel */ if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_TRIGGER], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, - DataLength) != HAL_OK) + DataLength) != HAL_OK) { + /* Return error status */ return HAL_ERROR; } break; @@ -4614,7 +4662,6 @@ HAL_StatusTypeDef HAL_TIM_DMABurst_MultiReadStart(TIM_HandleTypeDef *htim, uint3 */ HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStop(TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc) { - HAL_StatusTypeDef status = HAL_OK; /* Check the parameters */ assert_param(IS_TIM_DMA_SOURCE(BurstRequestSrc)); @@ -4655,17 +4702,14 @@ HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStop(TIM_HandleTypeDef *htim, uint32_t Bu break; } - if (HAL_OK == status) - { - /* Disable the TIM Update DMA request */ - __HAL_TIM_DISABLE_DMA(htim, BurstRequestSrc); - } + /* Disable the TIM Update DMA request */ + __HAL_TIM_DISABLE_DMA(htim, BurstRequestSrc); /* Change the DMA burst operation state */ htim->DMABurstState = HAL_DMA_BURST_STATE_READY; /* Return function status */ - return status; + return HAL_OK; } /** @@ -5602,91 +5646,113 @@ HAL_StatusTypeDef HAL_TIM_UnRegisterCallback(TIM_HandleTypeDef *htim, HAL_TIM_Ca switch (CallbackID) { case HAL_TIM_BASE_MSPINIT_CB_ID : - htim->Base_MspInitCallback = HAL_TIM_Base_MspInit; /* Legacy weak Base MspInit Callback */ + /* Legacy weak Base MspInit Callback */ + htim->Base_MspInitCallback = HAL_TIM_Base_MspInit; break; case HAL_TIM_BASE_MSPDEINIT_CB_ID : - htim->Base_MspDeInitCallback = HAL_TIM_Base_MspDeInit; /* Legacy weak Base Msp DeInit Callback */ + /* Legacy weak Base Msp DeInit Callback */ + htim->Base_MspDeInitCallback = HAL_TIM_Base_MspDeInit; break; case HAL_TIM_IC_MSPINIT_CB_ID : - htim->IC_MspInitCallback = HAL_TIM_IC_MspInit; /* Legacy weak IC Msp Init Callback */ + /* Legacy weak IC Msp Init Callback */ + htim->IC_MspInitCallback = HAL_TIM_IC_MspInit; break; case HAL_TIM_IC_MSPDEINIT_CB_ID : - htim->IC_MspDeInitCallback = HAL_TIM_IC_MspDeInit; /* Legacy weak IC Msp DeInit Callback */ + /* Legacy weak IC Msp DeInit Callback */ + htim->IC_MspDeInitCallback = HAL_TIM_IC_MspDeInit; break; case HAL_TIM_OC_MSPINIT_CB_ID : - htim->OC_MspInitCallback = HAL_TIM_OC_MspInit; /* Legacy weak OC Msp Init Callback */ + /* Legacy weak OC Msp Init Callback */ + htim->OC_MspInitCallback = HAL_TIM_OC_MspInit; break; case HAL_TIM_OC_MSPDEINIT_CB_ID : - htim->OC_MspDeInitCallback = HAL_TIM_OC_MspDeInit; /* Legacy weak OC Msp DeInit Callback */ + /* Legacy weak OC Msp DeInit Callback */ + htim->OC_MspDeInitCallback = HAL_TIM_OC_MspDeInit; break; case HAL_TIM_PWM_MSPINIT_CB_ID : - htim->PWM_MspInitCallback = HAL_TIM_PWM_MspInit; /* Legacy weak PWM Msp Init Callback */ + /* Legacy weak PWM Msp Init Callback */ + htim->PWM_MspInitCallback = HAL_TIM_PWM_MspInit; break; case HAL_TIM_PWM_MSPDEINIT_CB_ID : - htim->PWM_MspDeInitCallback = HAL_TIM_PWM_MspDeInit; /* Legacy weak PWM Msp DeInit Callback */ + /* Legacy weak PWM Msp DeInit Callback */ + htim->PWM_MspDeInitCallback = HAL_TIM_PWM_MspDeInit; break; case HAL_TIM_ONE_PULSE_MSPINIT_CB_ID : - htim->OnePulse_MspInitCallback = HAL_TIM_OnePulse_MspInit; /* Legacy weak One Pulse Msp Init Callback */ + /* Legacy weak One Pulse Msp Init Callback */ + htim->OnePulse_MspInitCallback = HAL_TIM_OnePulse_MspInit; break; case HAL_TIM_ONE_PULSE_MSPDEINIT_CB_ID : - htim->OnePulse_MspDeInitCallback = HAL_TIM_OnePulse_MspDeInit; /* Legacy weak One Pulse Msp DeInit Callback */ + /* Legacy weak One Pulse Msp DeInit Callback */ + htim->OnePulse_MspDeInitCallback = HAL_TIM_OnePulse_MspDeInit; break; case HAL_TIM_ENCODER_MSPINIT_CB_ID : - htim->Encoder_MspInitCallback = HAL_TIM_Encoder_MspInit; /* Legacy weak Encoder Msp Init Callback */ + /* Legacy weak Encoder Msp Init Callback */ + htim->Encoder_MspInitCallback = HAL_TIM_Encoder_MspInit; break; case HAL_TIM_ENCODER_MSPDEINIT_CB_ID : - htim->Encoder_MspDeInitCallback = HAL_TIM_Encoder_MspDeInit; /* Legacy weak Encoder Msp DeInit Callback */ + /* Legacy weak Encoder Msp DeInit Callback */ + htim->Encoder_MspDeInitCallback = HAL_TIM_Encoder_MspDeInit; break; case HAL_TIM_PERIOD_ELAPSED_CB_ID : - htim->PeriodElapsedCallback = HAL_TIM_PeriodElapsedCallback; /* Legacy weak Period Elapsed Callback */ + /* Legacy weak Period Elapsed Callback */ + htim->PeriodElapsedCallback = HAL_TIM_PeriodElapsedCallback; break; case HAL_TIM_PERIOD_ELAPSED_HALF_CB_ID : - htim->PeriodElapsedHalfCpltCallback = HAL_TIM_PeriodElapsedHalfCpltCallback; /* Legacy weak Period Elapsed half complete Callback */ + /* Legacy weak Period Elapsed half complete Callback */ + htim->PeriodElapsedHalfCpltCallback = HAL_TIM_PeriodElapsedHalfCpltCallback; break; case HAL_TIM_TRIGGER_CB_ID : - htim->TriggerCallback = HAL_TIM_TriggerCallback; /* Legacy weak Trigger Callback */ + /* Legacy weak Trigger Callback */ + htim->TriggerCallback = HAL_TIM_TriggerCallback; break; case HAL_TIM_TRIGGER_HALF_CB_ID : - htim->TriggerHalfCpltCallback = HAL_TIM_TriggerHalfCpltCallback; /* Legacy weak Trigger half complete Callback */ + /* Legacy weak Trigger half complete Callback */ + htim->TriggerHalfCpltCallback = HAL_TIM_TriggerHalfCpltCallback; break; case HAL_TIM_IC_CAPTURE_CB_ID : - htim->IC_CaptureCallback = HAL_TIM_IC_CaptureCallback; /* Legacy weak IC Capture Callback */ + /* Legacy weak IC Capture Callback */ + htim->IC_CaptureCallback = HAL_TIM_IC_CaptureCallback; break; case HAL_TIM_IC_CAPTURE_HALF_CB_ID : - htim->IC_CaptureHalfCpltCallback = HAL_TIM_IC_CaptureHalfCpltCallback; /* Legacy weak IC Capture half complete Callback */ + /* Legacy weak IC Capture half complete Callback */ + htim->IC_CaptureHalfCpltCallback = HAL_TIM_IC_CaptureHalfCpltCallback; break; case HAL_TIM_OC_DELAY_ELAPSED_CB_ID : - htim->OC_DelayElapsedCallback = HAL_TIM_OC_DelayElapsedCallback; /* Legacy weak OC Delay Elapsed Callback */ + /* Legacy weak OC Delay Elapsed Callback */ + htim->OC_DelayElapsedCallback = HAL_TIM_OC_DelayElapsedCallback; break; case HAL_TIM_PWM_PULSE_FINISHED_CB_ID : - htim->PWM_PulseFinishedCallback = HAL_TIM_PWM_PulseFinishedCallback; /* Legacy weak PWM Pulse Finished Callback */ + /* Legacy weak PWM Pulse Finished Callback */ + htim->PWM_PulseFinishedCallback = HAL_TIM_PWM_PulseFinishedCallback; break; case HAL_TIM_PWM_PULSE_FINISHED_HALF_CB_ID : - htim->PWM_PulseFinishedHalfCpltCallback = HAL_TIM_PWM_PulseFinishedHalfCpltCallback; /* Legacy weak PWM Pulse Finished half complete Callback */ + /* Legacy weak PWM Pulse Finished half complete Callback */ + htim->PWM_PulseFinishedHalfCpltCallback = HAL_TIM_PWM_PulseFinishedHalfCpltCallback; break; case HAL_TIM_ERROR_CB_ID : - htim->ErrorCallback = HAL_TIM_ErrorCallback; /* Legacy weak Error Callback */ + /* Legacy weak Error Callback */ + htim->ErrorCallback = HAL_TIM_ErrorCallback; break; default : @@ -5700,51 +5766,63 @@ HAL_StatusTypeDef HAL_TIM_UnRegisterCallback(TIM_HandleTypeDef *htim, HAL_TIM_Ca switch (CallbackID) { case HAL_TIM_BASE_MSPINIT_CB_ID : - htim->Base_MspInitCallback = HAL_TIM_Base_MspInit; /* Legacy weak Base MspInit Callback */ + /* Legacy weak Base MspInit Callback */ + htim->Base_MspInitCallback = HAL_TIM_Base_MspInit; break; case HAL_TIM_BASE_MSPDEINIT_CB_ID : - htim->Base_MspDeInitCallback = HAL_TIM_Base_MspDeInit; /* Legacy weak Base Msp DeInit Callback */ + /* Legacy weak Base Msp DeInit Callback */ + htim->Base_MspDeInitCallback = HAL_TIM_Base_MspDeInit; break; case HAL_TIM_IC_MSPINIT_CB_ID : - htim->IC_MspInitCallback = HAL_TIM_IC_MspInit; /* Legacy weak IC Msp Init Callback */ + /* Legacy weak IC Msp Init Callback */ + htim->IC_MspInitCallback = HAL_TIM_IC_MspInit; break; case HAL_TIM_IC_MSPDEINIT_CB_ID : - htim->IC_MspDeInitCallback = HAL_TIM_IC_MspDeInit; /* Legacy weak IC Msp DeInit Callback */ + /* Legacy weak IC Msp DeInit Callback */ + htim->IC_MspDeInitCallback = HAL_TIM_IC_MspDeInit; break; case HAL_TIM_OC_MSPINIT_CB_ID : - htim->OC_MspInitCallback = HAL_TIM_OC_MspInit; /* Legacy weak OC Msp Init Callback */ + /* Legacy weak OC Msp Init Callback */ + htim->OC_MspInitCallback = HAL_TIM_OC_MspInit; break; case HAL_TIM_OC_MSPDEINIT_CB_ID : - htim->OC_MspDeInitCallback = HAL_TIM_OC_MspDeInit; /* Legacy weak OC Msp DeInit Callback */ + /* Legacy weak OC Msp DeInit Callback */ + htim->OC_MspDeInitCallback = HAL_TIM_OC_MspDeInit; break; case HAL_TIM_PWM_MSPINIT_CB_ID : - htim->PWM_MspInitCallback = HAL_TIM_PWM_MspInit; /* Legacy weak PWM Msp Init Callback */ + /* Legacy weak PWM Msp Init Callback */ + htim->PWM_MspInitCallback = HAL_TIM_PWM_MspInit; break; case HAL_TIM_PWM_MSPDEINIT_CB_ID : - htim->PWM_MspDeInitCallback = HAL_TIM_PWM_MspDeInit; /* Legacy weak PWM Msp DeInit Callback */ + /* Legacy weak PWM Msp DeInit Callback */ + htim->PWM_MspDeInitCallback = HAL_TIM_PWM_MspDeInit; break; case HAL_TIM_ONE_PULSE_MSPINIT_CB_ID : - htim->OnePulse_MspInitCallback = HAL_TIM_OnePulse_MspInit; /* Legacy weak One Pulse Msp Init Callback */ + /* Legacy weak One Pulse Msp Init Callback */ + htim->OnePulse_MspInitCallback = HAL_TIM_OnePulse_MspInit; break; case HAL_TIM_ONE_PULSE_MSPDEINIT_CB_ID : - htim->OnePulse_MspDeInitCallback = HAL_TIM_OnePulse_MspDeInit; /* Legacy weak One Pulse Msp DeInit Callback */ + /* Legacy weak One Pulse Msp DeInit Callback */ + htim->OnePulse_MspDeInitCallback = HAL_TIM_OnePulse_MspDeInit; break; case HAL_TIM_ENCODER_MSPINIT_CB_ID : - htim->Encoder_MspInitCallback = HAL_TIM_Encoder_MspInit; /* Legacy weak Encoder Msp Init Callback */ + /* Legacy weak Encoder Msp Init Callback */ + htim->Encoder_MspInitCallback = HAL_TIM_Encoder_MspInit; break; case HAL_TIM_ENCODER_MSPDEINIT_CB_ID : - htim->Encoder_MspDeInitCallback = HAL_TIM_Encoder_MspDeInit; /* Legacy weak Encoder Msp DeInit Callback */ + /* Legacy weak Encoder Msp DeInit Callback */ + htim->Encoder_MspDeInitCallback = HAL_TIM_Encoder_MspDeInit; break; default : @@ -5871,12 +5949,12 @@ HAL_TIM_ActiveChannel HAL_TIM_GetActiveChannel(TIM_HandleTypeDef *htim) HAL_TIM_ChannelStateTypeDef HAL_TIM_GetChannelState(TIM_HandleTypeDef *htim, uint32_t Channel) { HAL_TIM_ChannelStateTypeDef channel_state; - + /* Check the parameters */ assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); channel_state = TIM_CHANNEL_STATE_GET(htim, Channel); - + return channel_state; } @@ -5889,7 +5967,7 @@ HAL_TIM_DMABurstStateTypeDef HAL_TIM_DMABurstState(TIM_HandleTypeDef *htim) { /* Check the parameters */ assert_param(IS_TIM_DMABURST_INSTANCE(htim->Instance)); - + return htim->DMABurstState; } @@ -5953,14 +6031,14 @@ void TIM_DMAError(DMA_HandleTypeDef *hdma) * @param hdma pointer to DMA handle. * @retval None */ -void TIM_DMADelayPulseCplt(DMA_HandleTypeDef *hdma) +static void TIM_DMADelayPulseCplt(DMA_HandleTypeDef *hdma) { TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; if (hdma == htim->hdma[TIM_DMA_ID_CC1]) { htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1; - + if (hdma->Init.Mode == DMA_NORMAL) { TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); @@ -5969,7 +6047,7 @@ void TIM_DMADelayPulseCplt(DMA_HandleTypeDef *hdma) else if (hdma == htim->hdma[TIM_DMA_ID_CC2]) { htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2; - + if (hdma->Init.Mode == DMA_NORMAL) { TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY); @@ -5978,7 +6056,7 @@ void TIM_DMADelayPulseCplt(DMA_HandleTypeDef *hdma) else if (hdma == htim->hdma[TIM_DMA_ID_CC3]) { htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3; - + if (hdma->Init.Mode == DMA_NORMAL) { TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_3, HAL_TIM_CHANNEL_STATE_READY); @@ -5987,7 +6065,7 @@ void TIM_DMADelayPulseCplt(DMA_HandleTypeDef *hdma) else if (hdma == htim->hdma[TIM_DMA_ID_CC4]) { htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4; - + if (hdma->Init.Mode == DMA_NORMAL) { TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_4, HAL_TIM_CHANNEL_STATE_READY); @@ -6012,7 +6090,7 @@ void TIM_DMADelayPulseCplt(DMA_HandleTypeDef *hdma) * @param hdma pointer to DMA handle. * @retval None */ -void TIM_DMADelayPulseHalfCplt(DMA_HandleTypeDef *hdma) +static void TIM_DMADelayPulseHalfCplt(DMA_HandleTypeDef *hdma) { TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; @@ -6058,7 +6136,7 @@ void TIM_DMACaptureCplt(DMA_HandleTypeDef *hdma) if (hdma == htim->hdma[TIM_DMA_ID_CC1]) { htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1; - + if (hdma->Init.Mode == DMA_NORMAL) { TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); @@ -6067,7 +6145,7 @@ void TIM_DMACaptureCplt(DMA_HandleTypeDef *hdma) else if (hdma == htim->hdma[TIM_DMA_ID_CC2]) { htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2; - + if (hdma->Init.Mode == DMA_NORMAL) { TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY); @@ -6076,7 +6154,7 @@ void TIM_DMACaptureCplt(DMA_HandleTypeDef *hdma) else if (hdma == htim->hdma[TIM_DMA_ID_CC3]) { htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3; - + if (hdma->Init.Mode == DMA_NORMAL) { TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_3, HAL_TIM_CHANNEL_STATE_READY); @@ -6085,7 +6163,7 @@ void TIM_DMACaptureCplt(DMA_HandleTypeDef *hdma) else if (hdma == htim->hdma[TIM_DMA_ID_CC4]) { htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4; - + if (hdma->Init.Mode == DMA_NORMAL) { TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_4, HAL_TIM_CHANNEL_STATE_READY); @@ -6224,7 +6302,7 @@ static void TIM_DMATriggerHalfCplt(DMA_HandleTypeDef *hdma) * @param Structure TIM Base configuration structure * @retval None */ -void TIM_Base_SetConfig(TIM_TypeDef *TIMx, TIM_Base_InitTypeDef *Structure) +static void TIM_Base_SetConfig(TIM_TypeDef *TIMx, TIM_Base_InitTypeDef *Structure) { uint32_t tmpcr1; tmpcr1 = TIMx->CR1; @@ -6938,16 +7016,16 @@ static void TIM_CCxChannelCmd(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t Chan void TIM_ResetCallback(TIM_HandleTypeDef *htim) { /* Reset the TIM callback to the legacy weak callbacks */ - htim->PeriodElapsedCallback = HAL_TIM_PeriodElapsedCallback; /* Legacy weak PeriodElapsedCallback */ - htim->PeriodElapsedHalfCpltCallback = HAL_TIM_PeriodElapsedHalfCpltCallback; /* Legacy weak PeriodElapsedHalfCpltCallback */ - htim->TriggerCallback = HAL_TIM_TriggerCallback; /* Legacy weak TriggerCallback */ - htim->TriggerHalfCpltCallback = HAL_TIM_TriggerHalfCpltCallback; /* Legacy weak TriggerHalfCpltCallback */ - htim->IC_CaptureCallback = HAL_TIM_IC_CaptureCallback; /* Legacy weak IC_CaptureCallback */ - htim->IC_CaptureHalfCpltCallback = HAL_TIM_IC_CaptureHalfCpltCallback; /* Legacy weak IC_CaptureHalfCpltCallback */ - htim->OC_DelayElapsedCallback = HAL_TIM_OC_DelayElapsedCallback; /* Legacy weak OC_DelayElapsedCallback */ - htim->PWM_PulseFinishedCallback = HAL_TIM_PWM_PulseFinishedCallback; /* Legacy weak PWM_PulseFinishedCallback */ - htim->PWM_PulseFinishedHalfCpltCallback = HAL_TIM_PWM_PulseFinishedHalfCpltCallback; /* Legacy weak PWM_PulseFinishedHalfCpltCallback */ - htim->ErrorCallback = HAL_TIM_ErrorCallback; /* Legacy weak ErrorCallback */ + htim->PeriodElapsedCallback = HAL_TIM_PeriodElapsedCallback; + htim->PeriodElapsedHalfCpltCallback = HAL_TIM_PeriodElapsedHalfCpltCallback; + htim->TriggerCallback = HAL_TIM_TriggerCallback; + htim->TriggerHalfCpltCallback = HAL_TIM_TriggerHalfCpltCallback; + htim->IC_CaptureCallback = HAL_TIM_IC_CaptureCallback; + htim->IC_CaptureHalfCpltCallback = HAL_TIM_IC_CaptureHalfCpltCallback; + htim->OC_DelayElapsedCallback = HAL_TIM_OC_DelayElapsedCallback; + htim->PWM_PulseFinishedCallback = HAL_TIM_PWM_PulseFinishedCallback; + htim->PWM_PulseFinishedHalfCpltCallback = HAL_TIM_PWM_PulseFinishedHalfCpltCallback; + htim->ErrorCallback = HAL_TIM_ErrorCallback; } #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ diff --git a/cubemx/voc-sensor.ioc b/cubemx/voc-sensor.ioc index 9e324e3..cc9bd02 100644 --- a/cubemx/voc-sensor.ioc +++ b/cubemx/voc-sensor.ioc @@ -1,153 +1,153 @@ #MicroXplorer Configuration settings - do not modify -Mcu.Family=STM32L1 -RCC.MSI_VALUE=2097000 +Dma.Request0=SPI2_RX +Dma.Request1=SPI2_TX +Dma.RequestsNb=2 +Dma.SPI2_RX.0.Direction=DMA_PERIPH_TO_MEMORY Dma.SPI2_RX.0.Instance=DMA1_Channel4 -ProjectManager.MainLocation=Core/Src -Dma.SPI2_TX.1.MemInc=DMA_MINC_ENABLE -ProjectManager.ProjectFileName=voc-sensor.ioc -Dma.SPI2_RX.0.RequestParameters=Instance,Direction,PeriphInc,MemInc,PeriphDataAlignment,MemDataAlignment,Mode,Priority -FREERTOS.Tasks01=defaultTask,24,128,StartDefaultTask,Default,NULL,Dynamic,NULL,NULL;sensor,24,512,sensorTask,As external,NULL,Dynamic,NULL,NULL -NVIC.DMA1_Channel5_IRQn=true\:5\:0\:true\:false\:true\:false\:false\:true -ProjectManager.KeepUserCode=true -Mcu.PinsNb=8 -Mcu.UserName=STM32L152RCTx -SPI2.VirtualType=VM_MASTER -ProjectManager.NoMain=false +Dma.SPI2_RX.0.MemDataAlignment=DMA_MDATAALIGN_BYTE +Dma.SPI2_RX.0.MemInc=DMA_MINC_ENABLE Dma.SPI2_RX.0.Mode=DMA_NORMAL -NVIC.SavedSvcallIrqHandlerGenerated=true -RCC.PLLCLKFreq_Value=32000000 -FREERTOS.configCHECK_FOR_STACK_OVERFLOW=2 -ProjectManager.functionlistsort=1-MX_GPIO_Init-GPIO-false-HAL-true,2-MX_DMA_Init-DMA-false-HAL-true,3-SystemClock_Config-RCC-false-HAL-false,4-MX_SPI2_Init-SPI2-false-HAL-true +Dma.SPI2_RX.0.PeriphDataAlignment=DMA_PDATAALIGN_BYTE +Dma.SPI2_RX.0.PeriphInc=DMA_PINC_DISABLE +Dma.SPI2_RX.0.Priority=DMA_PRIORITY_LOW +Dma.SPI2_RX.0.RequestParameters=Instance,Direction,PeriphInc,MemInc,PeriphDataAlignment,MemDataAlignment,Mode,Priority +Dma.SPI2_TX.1.Direction=DMA_MEMORY_TO_PERIPH +Dma.SPI2_TX.1.Instance=DMA1_Channel5 +Dma.SPI2_TX.1.MemDataAlignment=DMA_MDATAALIGN_BYTE +Dma.SPI2_TX.1.MemInc=DMA_MINC_ENABLE +Dma.SPI2_TX.1.Mode=DMA_NORMAL +Dma.SPI2_TX.1.PeriphDataAlignment=DMA_PDATAALIGN_BYTE Dma.SPI2_TX.1.PeriphInc=DMA_PINC_DISABLE -RCC.RTCFreq_Value=37000 -ProjectManager.DefaultFWLocation=true -PB12.Locked=true -NVIC.SVC_IRQn=true\:0\:0\:false\:false\:false\:false\:false\:false -ProjectManager.DeletePrevious=true -RCC.TimerFreq_Value=32000000 -PB15.Signal=SPI2_MOSI -PB13.Signal=SPI2_SCK -PinOutPanel.RotationAngle=0 -RCC.FamilyName=M -RCC.SYSCLKSource=RCC_SYSCLKSOURCE_PLLCLK -ProjectManager.StackSize=0x400 -VP_FREERTOS_VS_CMSIS_V2.Mode=CMSIS_V2 +Dma.SPI2_TX.1.Priority=DMA_PRIORITY_LOW Dma.SPI2_TX.1.RequestParameters=Instance,Direction,PeriphInc,MemInc,PeriphDataAlignment,MemDataAlignment,Mode,Priority -PA13.Signal=SYS_JTMS-SWDIO -Mcu.IP4=SPI2 -RCC.FCLKCortexFreq_Value=32000000 -Mcu.IP5=SYS -Mcu.IP2=NVIC -Mcu.IP3=RCC +FREERTOS.FootprintOK=true +FREERTOS.HEAP_NUMBER=1 +FREERTOS.IPParameters=Tasks01,configCHECK_FOR_STACK_OVERFLOW,FootprintOK,HEAP_NUMBER +FREERTOS.Tasks01=defaultTask,24,128,StartDefaultTask,Default,NULL,Dynamic,NULL,NULL;sensor,24,512,sensorTask,As external,NULL,Dynamic,NULL,NULL +FREERTOS.configCHECK_FOR_STACK_OVERFLOW=2 +File.Version=6 +GPIO.groupedBy= +KeepUserPlacement=false +Mcu.Family=STM32L1 Mcu.IP0=DMA Mcu.IP1=FREERTOS -Dma.SPI2_RX.0.PeriphDataAlignment=DMA_PDATAALIGN_BYTE -Mcu.UserConstants= -ProjectManager.TargetToolchain=Makefile -Mcu.ThirdPartyNb=0 -RCC.HCLKFreq_Value=32000000 +Mcu.IP2=NVIC +Mcu.IP3=RCC +Mcu.IP4=SPI2 +Mcu.IP5=SYS Mcu.IPNb=6 -ProjectManager.PreviousToolchain= -RCC.APB2TimFreq_Value=32000000 -SPI2.IPParameters=VirtualType,Mode,Direction,CalculateBaudRate,BaudRatePrescaler -Mcu.Pin6=VP_FREERTOS_VS_CMSIS_V2 -Mcu.Pin7=VP_SYS_VS_tim2 -ProjectManager.RegisterCallBack= -FREERTOS.IPParameters=Tasks01,configCHECK_FOR_STACK_OVERFLOW,FootprintOK,HEAP_NUMBER -RCC.LSE_VALUE=32768 -RCC.AHBFreq_Value=32000000 -SPI2.BaudRatePrescaler=SPI_BAUDRATEPRESCALER_4 +Mcu.Name=STM32L152RCTx +Mcu.Package=LQFP64 Mcu.Pin0=PB12 Mcu.Pin1=PB13 -GPIO.groupedBy= Mcu.Pin2=PB14 Mcu.Pin3=PB15 Mcu.Pin4=PA13 -PB14.Signal=SPI2_MISO Mcu.Pin5=PA14 -ProjectManager.ProjectBuild=false -RCC.HSE_VALUE=24000000 -NVIC.UsageFault_IRQn=true\:0\:0\:false\:false\:true\:false\:false\:false -NVIC.DebugMonitor_IRQn=true\:0\:0\:false\:false\:true\:false\:false\:false -RCC.MCOPinFreq_Value=32000000 -board=custom -Dma.SPI2_TX.1.Direction=DMA_MEMORY_TO_PERIPH -RCC.VCOOutputFreq_Value=64000000 -NVIC.SysTick_IRQn=true\:0\:0\:false\:false\:false\:false\:false\:false -ProjectManager.LastFirmware=true -RCC.PLLMUL=RCC_PLL_MUL4 -PB15.Mode=Full_Duplex_Master -PB12.GPIO_Label=SPI_CS -ProjectManager.FirmwarePackage=STM32Cube FW_L1 V1.10.2 -MxDb.Version=DB.6.0.0 -NVIC.SavedSystickIrqHandlerGenerated=true -RCC.APB2Freq_Value=32000000 -ProjectManager.BackupPrevious=false -Dma.SPI2_TX.1.PeriphDataAlignment=DMA_PDATAALIGN_BYTE -MxCube.Version=6.0.1 -VP_SYS_VS_tim2.Signal=SYS_VS_tim2 -PA14.Mode=Serial_Wire -Dma.SPI2_TX.1.Priority=DMA_PRIORITY_LOW -PB14.Mode=Full_Duplex_Master -FREERTOS.HEAP_NUMBER=1 -NVIC.TIM2_IRQn=true\:0\:0\:false\:false\:true\:false\:false\:true -File.Version=6 -SPI2.CalculateBaudRate=8.0 MBits/s -Dma.SPI2_RX.0.MemDataAlignment=DMA_MDATAALIGN_BYTE -NVIC.NonMaskableInt_IRQn=true\:0\:0\:false\:false\:true\:false\:false\:false -NVIC.PendSV_IRQn=true\:0\:0\:false\:false\:false\:false\:false\:false -PA13.Mode=Serial_Wire -Dma.SPI2_RX.0.Priority=DMA_PRIORITY_LOW -ProjectManager.FreePins=true -RCC.IPParameters=48MHZClocksFreq_Value,AHBFreq_Value,APB1Freq_Value,APB1TimFreq_Value,APB2Freq_Value,APB2TimFreq_Value,FCLKCortexFreq_Value,FamilyName,HCLKFreq_Value,HSE_VALUE,HSI_VALUE,LSE_VALUE,LSI_VALUE,MCOPinFreq_Value,MSI_VALUE,PLLCLKFreq_Value,PLLMUL,PWRFreq_Value,RTCFreq_Value,RTCHSEDivFreq_Value,SYSCLKFreq_VALUE,SYSCLKSource,TIMFreq_Value,TimerFreq_Value,VCOOutputFreq_Value -ProjectManager.AskForMigrate=true -Mcu.Name=STM32L152RCTx -Dma.RequestsNb=2 -ProjectManager.HalAssertFull=false -NVIC.SavedPendsvIrqHandlerGenerated=true -Dma.SPI2_RX.0.MemInc=DMA_MINC_ENABLE -RCC.RTCHSEDivFreq_Value=12000000 -ProjectManager.ProjectName=voc-sensor -ProjectManager.UnderRoot=false -VP_FREERTOS_VS_CMSIS_V2.Signal=FREERTOS_VS_CMSIS_V2 -ProjectManager.CoupleFile=true -RCC.48MHZClocksFreq_Value=32000000 -RCC.SYSCLKFreq_VALUE=32000000 -Mcu.Package=LQFP64 -VP_SYS_VS_tim2.Mode=TIM2 -Dma.SPI2_TX.1.Mode=DMA_NORMAL -NVIC.TimeBase=TIM2_IRQn -SPI2.Mode=SPI_MODE_MASTER -NVIC.ForceEnableDMAVector=true -KeepUserPlacement=false -Dma.SPI2_RX.0.PeriphInc=DMA_PINC_DISABLE -NVIC.MemoryManagement_IRQn=true\:0\:0\:false\:false\:true\:false\:false\:false -ProjectManager.CompilerOptimize=6 -ProjectManager.ToolChainLocation= -RCC.LSI_VALUE=37000 -NVIC.TimeBaseIP=TIM2 -PA14.Signal=SYS_JTCK-SWCLK -FREERTOS.FootprintOK=true -ProjectManager.HeapSize=0x200 -NVIC.HardFault_IRQn=true\:0\:0\:false\:false\:true\:false\:false\:false -Dma.SPI2_TX.1.Instance=DMA1_Channel5 -ProjectManager.ComputerToolchain=false -RCC.HSI_VALUE=16000000 -NVIC.PriorityGroup=NVIC_PRIORITYGROUP_4 -Dma.Request1=SPI2_TX -RCC.APB1TimFreq_Value=32000000 +Mcu.Pin6=VP_FREERTOS_VS_CMSIS_V2 +Mcu.Pin7=VP_SYS_VS_tim2 +Mcu.PinsNb=8 +Mcu.ThirdPartyNb=0 +Mcu.UserConstants= +Mcu.UserName=STM32L152RCTx +MxCube.Version=6.3.0 +MxDb.Version=DB.6.0.30 NVIC.BusFault_IRQn=true\:0\:0\:false\:false\:true\:false\:false\:false -RCC.PWRFreq_Value=32000000 -SPI2.Direction=SPI_DIRECTION_2LINES -Dma.SPI2_RX.0.Direction=DMA_PERIPH_TO_MEMORY -PB13.Mode=Full_Duplex_Master NVIC.DMA1_Channel4_IRQn=true\:5\:0\:true\:false\:true\:false\:false\:true -RCC.APB1Freq_Value=32000000 -Dma.Request0=SPI2_RX -Dma.SPI2_TX.1.MemDataAlignment=DMA_MDATAALIGN_BYTE -ProjectManager.CustomerFirmwarePackage= -ProjectManager.DeviceId=STM32L152RCTx +NVIC.DMA1_Channel5_IRQn=true\:5\:0\:true\:false\:true\:false\:false\:true +NVIC.DebugMonitor_IRQn=true\:0\:0\:false\:false\:true\:false\:false\:false +NVIC.ForceEnableDMAVector=true +NVIC.HardFault_IRQn=true\:0\:0\:false\:false\:true\:false\:false\:false +NVIC.MemoryManagement_IRQn=true\:0\:0\:false\:false\:true\:false\:false\:false +NVIC.NonMaskableInt_IRQn=true\:0\:0\:false\:false\:true\:false\:false\:false +NVIC.PendSV_IRQn=true\:15\:0\:false\:false\:false\:true\:false\:false +NVIC.PriorityGroup=NVIC_PRIORITYGROUP_4 +NVIC.SVC_IRQn=true\:0\:0\:false\:false\:false\:false\:false\:false +NVIC.SavedPendsvIrqHandlerGenerated=true +NVIC.SavedSvcallIrqHandlerGenerated=true +NVIC.SavedSystickIrqHandlerGenerated=true +NVIC.SysTick_IRQn=true\:15\:0\:false\:false\:false\:true\:false\:true +NVIC.TIM2_IRQn=true\:0\:0\:false\:false\:true\:false\:false\:true +NVIC.TimeBase=TIM2_IRQn +NVIC.TimeBaseIP=TIM2 +NVIC.UsageFault_IRQn=true\:0\:0\:false\:false\:true\:false\:false\:false +PA13.Mode=Serial_Wire +PA13.Signal=SYS_JTMS-SWDIO +PA14.Mode=Serial_Wire +PA14.Signal=SYS_JTCK-SWCLK PB12.GPIOParameters=GPIO_Label +PB12.GPIO_Label=SPI_CS +PB12.Locked=true PB12.Signal=GPIO_Output +PB13.Mode=Full_Duplex_Master +PB13.Signal=SPI2_SCK +PB14.Mode=Full_Duplex_Master +PB14.Signal=SPI2_MISO +PB15.Mode=Full_Duplex_Master +PB15.Signal=SPI2_MOSI +PinOutPanel.RotationAngle=0 +ProjectManager.AskForMigrate=true +ProjectManager.BackupPrevious=false +ProjectManager.CompilerOptimize=6 +ProjectManager.ComputerToolchain=false +ProjectManager.CoupleFile=true +ProjectManager.CustomerFirmwarePackage= +ProjectManager.DefaultFWLocation=true +ProjectManager.DeletePrevious=true +ProjectManager.DeviceId=STM32L152RCTx +ProjectManager.FirmwarePackage=STM32Cube FW_L1 V1.10.3 +ProjectManager.FreePins=true +ProjectManager.HalAssertFull=false +ProjectManager.HeapSize=0x200 +ProjectManager.KeepUserCode=true +ProjectManager.LastFirmware=true ProjectManager.LibraryCopy=1 +ProjectManager.MainLocation=Core/Src +ProjectManager.NoMain=false +ProjectManager.PreviousToolchain= +ProjectManager.ProjectBuild=false +ProjectManager.ProjectFileName=voc-sensor.ioc +ProjectManager.ProjectName=voc-sensor +ProjectManager.RegisterCallBack= +ProjectManager.StackSize=0x400 +ProjectManager.TargetToolchain=Makefile +ProjectManager.ToolChainLocation= +ProjectManager.UnderRoot=false +ProjectManager.functionlistsort=1-MX_GPIO_Init-GPIO-false-HAL-true,2-MX_DMA_Init-DMA-false-HAL-true,3-SystemClock_Config-RCC-false-HAL-false,4-MX_SPI2_Init-SPI2-false-HAL-true +RCC.48MHZClocksFreq_Value=32000000 +RCC.AHBFreq_Value=32000000 +RCC.APB1Freq_Value=32000000 +RCC.APB1TimFreq_Value=32000000 +RCC.APB2Freq_Value=32000000 +RCC.APB2TimFreq_Value=32000000 +RCC.FCLKCortexFreq_Value=32000000 +RCC.FamilyName=M +RCC.HCLKFreq_Value=32000000 +RCC.HSE_VALUE=24000000 +RCC.HSI_VALUE=16000000 +RCC.IPParameters=48MHZClocksFreq_Value,AHBFreq_Value,APB1Freq_Value,APB1TimFreq_Value,APB2Freq_Value,APB2TimFreq_Value,FCLKCortexFreq_Value,FamilyName,HCLKFreq_Value,HSE_VALUE,HSI_VALUE,LSE_VALUE,LSI_VALUE,MCOPinFreq_Value,MSI_VALUE,PLLCLKFreq_Value,PLLMUL,PWRFreq_Value,RTCFreq_Value,RTCHSEDivFreq_Value,SYSCLKFreq_VALUE,SYSCLKSource,TIMFreq_Value,TimerFreq_Value,VCOOutputFreq_Value +RCC.LSE_VALUE=32768 +RCC.LSI_VALUE=37000 +RCC.MCOPinFreq_Value=32000000 +RCC.MSI_VALUE=2097000 +RCC.PLLCLKFreq_Value=32000000 +RCC.PLLMUL=RCC_PLL_MUL4 +RCC.PWRFreq_Value=32000000 +RCC.RTCFreq_Value=37000 +RCC.RTCHSEDivFreq_Value=12000000 +RCC.SYSCLKFreq_VALUE=32000000 +RCC.SYSCLKSource=RCC_SYSCLKSOURCE_PLLCLK RCC.TIMFreq_Value=32000000 +RCC.TimerFreq_Value=32000000 +RCC.VCOOutputFreq_Value=64000000 +SPI2.BaudRatePrescaler=SPI_BAUDRATEPRESCALER_4 +SPI2.CalculateBaudRate=8.0 MBits/s +SPI2.Direction=SPI_DIRECTION_2LINES +SPI2.IPParameters=VirtualType,Mode,Direction,CalculateBaudRate,BaudRatePrescaler +SPI2.Mode=SPI_MODE_MASTER +SPI2.VirtualType=VM_MASTER +VP_FREERTOS_VS_CMSIS_V2.Mode=CMSIS_V2 +VP_FREERTOS_VS_CMSIS_V2.Signal=FREERTOS_VS_CMSIS_V2 +VP_SYS_VS_tim2.Mode=TIM2 +VP_SYS_VS_tim2.Signal=SYS_VS_tim2 +board=custom