409 lines
15 KiB
C
409 lines
15 KiB
C
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/**
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******************************************************************************
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* @file system_stm32l1xx.c
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* @author MCD Application Team
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* @brief CMSIS Cortex-M3 Device Peripheral Access Layer System Source File.
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*
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* This file provides two functions and one global variable to be called from
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* user application:
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* - SystemInit(): This function is called at startup just after reset and
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* before branch to main program. This call is made inside
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* the "startup_stm32l1xx.s" file.
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*
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* - SystemCoreClock variable: Contains the core clock (HCLK), it can be used
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* by the user application to setup the SysTick
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* timer or configure other parameters.
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*
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* - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must
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* be called whenever the core clock is changed
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* during program execution.
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*
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******************************************************************************
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* @attention
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*
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* <h2><center>© Copyright (c) 2017 STMicroelectronics.
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* All rights reserved.</center></h2>
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*
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* This software component is licensed by ST under BSD 3-Clause license,
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* the "License"; You may not use this file except in compliance with the
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* License. You may obtain a copy of the License at:
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* opensource.org/licenses/BSD-3-Clause
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*
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******************************************************************************
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*/
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/** @addtogroup CMSIS
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* @{
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*/
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/** @addtogroup stm32l1xx_system
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* @{
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*/
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/** @addtogroup STM32L1xx_System_Private_Includes
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* @{
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*/
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#include "stm32l1xx.h"
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/**
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* @}
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*/
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/** @addtogroup STM32L1xx_System_Private_TypesDefinitions
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* @{
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*/
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/**
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* @}
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*/
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/** @addtogroup STM32L1xx_System_Private_Defines
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* @{
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*/
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#if !defined (HSE_VALUE)
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#define HSE_VALUE ((uint32_t)8000000U) /*!< Default value of the External oscillator in Hz.
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This value can be provided and adapted by the user application. */
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#endif /* HSE_VALUE */
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#if !defined (HSI_VALUE)
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#define HSI_VALUE ((uint32_t)8000000U) /*!< Default value of the Internal oscillator in Hz.
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This value can be provided and adapted by the user application. */
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#endif /* HSI_VALUE */
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/*!< Uncomment the following line if you need to use external SRAM mounted
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on STM32L152D_EVAL board as data memory */
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/* #define DATA_IN_ExtSRAM */
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/*!< Uncomment the following line if you need to relocate your vector Table in
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Internal SRAM. */
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/* #define VECT_TAB_SRAM */
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#define VECT_TAB_OFFSET 0x00U /*!< Vector Table base offset field.
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This value must be a multiple of 0x200. */
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/**
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* @}
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*/
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/** @addtogroup STM32L1xx_System_Private_Macros
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* @{
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*/
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/**
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* @}
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*/
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/** @addtogroup STM32L1xx_System_Private_Variables
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* @{
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*/
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/* This variable is updated in three ways:
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1) by calling CMSIS function SystemCoreClockUpdate()
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2) by calling HAL API function HAL_RCC_GetHCLKFreq()
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3) each time HAL_RCC_ClockConfig() is called to configure the system clock frequency
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Note: If you use this function to configure the system clock; then there
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is no need to call the 2 first functions listed above, since SystemCoreClock
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variable is updated automatically.
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*/
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uint32_t SystemCoreClock = 2097000U;
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const uint8_t PLLMulTable[9] = {3U, 4U, 6U, 8U, 12U, 16U, 24U, 32U, 48U};
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const uint8_t AHBPrescTable[16] = {0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 1U, 2U, 3U, 4U, 6U, 7U, 8U, 9U};
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const uint8_t APBPrescTable[8] = {0U, 0U, 0U, 0U, 1U, 2U, 3U, 4U};
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/**
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* @}
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*/
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/** @addtogroup STM32L1xx_System_Private_FunctionPrototypes
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* @{
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*/
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#if defined (STM32L151xD) || defined (STM32L152xD) || defined (STM32L162xD)
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#ifdef DATA_IN_ExtSRAM
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static void SystemInit_ExtMemCtl(void);
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#endif /* DATA_IN_ExtSRAM */
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#endif /* STM32L151xD || STM32L152xD || STM32L162xD */
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/**
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* @}
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*/
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/** @addtogroup STM32L1xx_System_Private_Functions
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* @{
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*/
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/**
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* @brief Setup the microcontroller system.
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* Initialize the Embedded Flash Interface, the PLL and update the
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* SystemCoreClock variable.
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* @param None
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* @retval None
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*/
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void SystemInit (void)
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{
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#ifdef DATA_IN_ExtSRAM
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SystemInit_ExtMemCtl();
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#endif /* DATA_IN_ExtSRAM */
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#ifdef VECT_TAB_SRAM
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SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM. */
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#else
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SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH. */
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#endif
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}
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/**
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* @brief Update SystemCoreClock according to Clock Register Values
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* The SystemCoreClock variable contains the core clock (HCLK), it can
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* be used by the user application to setup the SysTick timer or configure
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* other parameters.
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*
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* @note Each time the core clock (HCLK) changes, this function must be called
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* to update SystemCoreClock variable value. Otherwise, any configuration
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* based on this variable will be incorrect.
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*
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* @note - The system frequency computed by this function is not the real
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* frequency in the chip. It is calculated based on the predefined
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* constant and the selected clock source:
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*
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* - If SYSCLK source is MSI, SystemCoreClock will contain the MSI
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* value as defined by the MSI range.
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*
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* - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(*)
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*
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* - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(**)
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*
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* - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(**)
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* or HSI_VALUE(*) multiplied/divided by the PLL factors.
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*
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* (*) HSI_VALUE is a constant defined in stm32l1xx.h file (default value
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* 16 MHz) but the real value may vary depending on the variations
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* in voltage and temperature.
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*
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* (**) HSE_VALUE is a constant defined in stm32l1xx.h file (default value
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* 8 MHz), user has to ensure that HSE_VALUE is same as the real
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* frequency of the crystal used. Otherwise, this function may
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* have wrong result.
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*
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* - The result of this function could be not correct when using fractional
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* value for HSE crystal.
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* @param None
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* @retval None
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*/
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void SystemCoreClockUpdate (void)
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{
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uint32_t tmp = 0, pllmul = 0, plldiv = 0, pllsource = 0, msirange = 0;
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/* Get SYSCLK source -------------------------------------------------------*/
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tmp = RCC->CFGR & RCC_CFGR_SWS;
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switch (tmp)
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{
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case 0x00: /* MSI used as system clock */
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msirange = (RCC->ICSCR & RCC_ICSCR_MSIRANGE) >> 13;
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SystemCoreClock = (32768 * (1 << (msirange + 1)));
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break;
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case 0x04: /* HSI used as system clock */
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SystemCoreClock = HSI_VALUE;
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break;
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case 0x08: /* HSE used as system clock */
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SystemCoreClock = HSE_VALUE;
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break;
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case 0x0C: /* PLL used as system clock */
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/* Get PLL clock source and multiplication factor ----------------------*/
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pllmul = RCC->CFGR & RCC_CFGR_PLLMUL;
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plldiv = RCC->CFGR & RCC_CFGR_PLLDIV;
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pllmul = PLLMulTable[(pllmul >> 18)];
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plldiv = (plldiv >> 22) + 1;
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pllsource = RCC->CFGR & RCC_CFGR_PLLSRC;
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if (pllsource == 0x00)
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{
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/* HSI oscillator clock selected as PLL clock entry */
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SystemCoreClock = (((HSI_VALUE) * pllmul) / plldiv);
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}
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else
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{
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/* HSE selected as PLL clock entry */
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SystemCoreClock = (((HSE_VALUE) * pllmul) / plldiv);
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}
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break;
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default: /* MSI used as system clock */
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msirange = (RCC->ICSCR & RCC_ICSCR_MSIRANGE) >> 13;
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SystemCoreClock = (32768 * (1 << (msirange + 1)));
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break;
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}
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/* Compute HCLK clock frequency --------------------------------------------*/
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/* Get HCLK prescaler */
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tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4)];
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/* HCLK clock frequency */
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SystemCoreClock >>= tmp;
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}
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#if defined (STM32L151xD) || defined (STM32L152xD) || defined (STM32L162xD)
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#ifdef DATA_IN_ExtSRAM
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/**
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* @brief Setup the external memory controller.
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* Called in SystemInit() function before jump to main.
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* This function configures the external SRAM mounted on STM32L152D_EVAL board
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* This SRAM will be used as program data memory (including heap and stack).
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* @param None
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* @retval None
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*/
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void SystemInit_ExtMemCtl(void)
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{
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__IO uint32_t tmpreg = 0;
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/* Flash 1 wait state */
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FLASH->ACR |= FLASH_ACR_LATENCY;
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/* Power enable */
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RCC->APB1ENR |= RCC_APB1ENR_PWREN;
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/* Delay after an RCC peripheral clock enabling */
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tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_PWREN);
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/* Select the Voltage Range 1 (1.8 V) */
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PWR->CR = PWR_CR_VOS_0;
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/* Wait Until the Voltage Regulator is ready */
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while((PWR->CSR & PWR_CSR_VOSF) != RESET)
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{
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}
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/*-- GPIOs Configuration -----------------------------------------------------*/
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/*
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+-------------------+--------------------+------------------+------------------+
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+ SRAM pins assignment +
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+-------------------+--------------------+------------------+------------------+
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| PD0 <-> FSMC_D2 | PE0 <-> FSMC_NBL0 | PF0 <-> FSMC_A0 | PG0 <-> FSMC_A10 |
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| PD1 <-> FSMC_D3 | PE1 <-> FSMC_NBL1 | PF1 <-> FSMC_A1 | PG1 <-> FSMC_A11 |
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| PD4 <-> FSMC_NOE | PE7 <-> FSMC_D4 | PF2 <-> FSMC_A2 | PG2 <-> FSMC_A12 |
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| PD5 <-> FSMC_NWE | PE8 <-> FSMC_D5 | PF3 <-> FSMC_A3 | PG3 <-> FSMC_A13 |
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| PD8 <-> FSMC_D13 | PE9 <-> FSMC_D6 | PF4 <-> FSMC_A4 | PG4 <-> FSMC_A14 |
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| PD9 <-> FSMC_D14 | PE10 <-> FSMC_D7 | PF5 <-> FSMC_A5 | PG5 <-> FSMC_A15 |
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| PD10 <-> FSMC_D15 | PE11 <-> FSMC_D8 | PF12 <-> FSMC_A6 | PG10<-> FSMC_NE2 |
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| PD11 <-> FSMC_A16 | PE12 <-> FSMC_D9 | PF13 <-> FSMC_A7 |------------------+
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| PD12 <-> FSMC_A17 | PE13 <-> FSMC_D10 | PF14 <-> FSMC_A8 |
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| PD13 <-> FSMC_A18 | PE14 <-> FSMC_D11 | PF15 <-> FSMC_A9 |
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| PD14 <-> FSMC_D0 | PE15 <-> FSMC_D12 |------------------+
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| PD15 <-> FSMC_D1 |--------------------+
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+-------------------+
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*/
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/* Enable GPIOD, GPIOE, GPIOF and GPIOG interface clock */
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RCC->AHBENR = 0x000080D8;
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/* Delay after an RCC peripheral clock enabling */
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tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_GPIODEN);
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/* Connect PDx pins to FSMC Alternate function */
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GPIOD->AFR[0] = 0x00CC00CC;
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GPIOD->AFR[1] = 0xCCCCCCCC;
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/* Configure PDx pins in Alternate function mode */
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GPIOD->MODER = 0xAAAA0A0A;
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/* Configure PDx pins speed to 40 MHz */
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GPIOD->OSPEEDR = 0xFFFF0F0F;
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/* Configure PDx pins Output type to push-pull */
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GPIOD->OTYPER = 0x00000000;
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/* No pull-up, pull-down for PDx pins */
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GPIOD->PUPDR = 0x00000000;
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/* Connect PEx pins to FSMC Alternate function */
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GPIOE->AFR[0] = 0xC00000CC;
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GPIOE->AFR[1] = 0xCCCCCCCC;
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/* Configure PEx pins in Alternate function mode */
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GPIOE->MODER = 0xAAAA800A;
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/* Configure PEx pins speed to 40 MHz */
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GPIOE->OSPEEDR = 0xFFFFC00F;
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/* Configure PEx pins Output type to push-pull */
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GPIOE->OTYPER = 0x00000000;
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/* No pull-up, pull-down for PEx pins */
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GPIOE->PUPDR = 0x00000000;
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/* Connect PFx pins to FSMC Alternate function */
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GPIOF->AFR[0] = 0x00CCCCCC;
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GPIOF->AFR[1] = 0xCCCC0000;
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/* Configure PFx pins in Alternate function mode */
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GPIOF->MODER = 0xAA000AAA;
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/* Configure PFx pins speed to 40 MHz */
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GPIOF->OSPEEDR = 0xFF000FFF;
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/* Configure PFx pins Output type to push-pull */
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GPIOF->OTYPER = 0x00000000;
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/* No pull-up, pull-down for PFx pins */
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GPIOF->PUPDR = 0x00000000;
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/* Connect PGx pins to FSMC Alternate function */
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GPIOG->AFR[0] = 0x00CCCCCC;
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GPIOG->AFR[1] = 0x00000C00;
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/* Configure PGx pins in Alternate function mode */
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GPIOG->MODER = 0x00200AAA;
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/* Configure PGx pins speed to 40 MHz */
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GPIOG->OSPEEDR = 0x00300FFF;
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/* Configure PGx pins Output type to push-pull */
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GPIOG->OTYPER = 0x00000000;
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/* No pull-up, pull-down for PGx pins */
|
||
|
|
GPIOG->PUPDR = 0x00000000;
|
||
|
|
|
||
|
|
/*-- FSMC Configuration ------------------------------------------------------*/
|
||
|
|
/* Enable the FSMC interface clock */
|
||
|
|
RCC->AHBENR = 0x400080D8;
|
||
|
|
|
||
|
|
/* Delay after an RCC peripheral clock enabling */
|
||
|
|
tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_FSMCEN);
|
||
|
|
|
||
|
|
(void)(tmpreg);
|
||
|
|
|
||
|
|
/* Configure and enable Bank1_SRAM3 */
|
||
|
|
FSMC_Bank1->BTCR[4] = 0x00001011;
|
||
|
|
FSMC_Bank1->BTCR[5] = 0x00000300;
|
||
|
|
FSMC_Bank1E->BWTR[4] = 0x0FFFFFFF;
|
||
|
|
/*
|
||
|
|
Bank1_SRAM3 is configured as follow:
|
||
|
|
|
||
|
|
p.FSMC_AddressSetupTime = 0;
|
||
|
|
p.FSMC_AddressHoldTime = 0;
|
||
|
|
p.FSMC_DataSetupTime = 3;
|
||
|
|
p.FSMC_BusTurnAroundDuration = 0;
|
||
|
|
p.FSMC_CLKDivision = 0;
|
||
|
|
p.FSMC_DataLatency = 0;
|
||
|
|
p.FSMC_AccessMode = FSMC_AccessMode_A;
|
||
|
|
|
||
|
|
FSMC_NORSRAMInitStructure.FSMC_Bank = FSMC_Bank1_NORSRAM3;
|
||
|
|
FSMC_NORSRAMInitStructure.FSMC_DataAddressMux = FSMC_DataAddressMux_Disable;
|
||
|
|
FSMC_NORSRAMInitStructure.FSMC_MemoryType = FSMC_MemoryType_SRAM;
|
||
|
|
FSMC_NORSRAMInitStructure.FSMC_MemoryDataWidth = FSMC_MemoryDataWidth_16b;
|
||
|
|
FSMC_NORSRAMInitStructure.FSMC_BurstAccessMode = FSMC_BurstAccessMode_Disable;
|
||
|
|
FSMC_NORSRAMInitStructure.FSMC_AsynchronousWait = FSMC_AsynchronousWait_Disable;
|
||
|
|
FSMC_NORSRAMInitStructure.FSMC_WaitSignalPolarity = FSMC_WaitSignalPolarity_Low;
|
||
|
|
FSMC_NORSRAMInitStructure.FSMC_WrapMode = FSMC_WrapMode_Disable;
|
||
|
|
FSMC_NORSRAMInitStructure.FSMC_WaitSignalActive = FSMC_WaitSignalActive_BeforeWaitState;
|
||
|
|
FSMC_NORSRAMInitStructure.FSMC_WriteOperation = FSMC_WriteOperation_Enable;
|
||
|
|
FSMC_NORSRAMInitStructure.FSMC_WaitSignal = FSMC_WaitSignal_Disable;
|
||
|
|
FSMC_NORSRAMInitStructure.FSMC_ExtendedMode = FSMC_ExtendedMode_Disable;
|
||
|
|
FSMC_NORSRAMInitStructure.FSMC_WriteBurst = FSMC_WriteBurst_Disable;
|
||
|
|
FSMC_NORSRAMInitStructure.FSMC_ReadWriteTimingStruct = &p;
|
||
|
|
FSMC_NORSRAMInitStructure.FSMC_WriteTimingStruct = &p;
|
||
|
|
|
||
|
|
FSMC_NORSRAMInit(&FSMC_NORSRAMInitStructure);
|
||
|
|
|
||
|
|
FSMC_NORSRAMCmd(FSMC_Bank1_NORSRAM3, ENABLE);
|
||
|
|
*/
|
||
|
|
|
||
|
|
}
|
||
|
|
#endif /* DATA_IN_ExtSRAM */
|
||
|
|
#endif /* STM32L151xD || STM32L152xD || STM32L162xD */
|
||
|
|
|
||
|
|
/**
|
||
|
|
* @}
|
||
|
|
*/
|
||
|
|
|
||
|
|
/**
|
||
|
|
* @}
|
||
|
|
*/
|
||
|
|
|
||
|
|
/**
|
||
|
|
* @}
|
||
|
|
*/
|
||
|
|
|
||
|
|
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|